git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-common32.dtsi

   1 /*
   2  * Device Tree Source commonly used by UniPhier ARM SoCs
   3  *
   4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         clocks {
  13                 refclk: ref {
  14                         #clock-cells = <0>;
  15                         compatible = "fixed-clock";
  16                 };
  17         };
  18
  19         soc: soc {
  20                 compatible = "simple-bus";
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 ranges;
  24                 interrupt-parent = <&intc>;
  25                 u-boot,dm-pre-reloc;
  26
  27                 serial0: serial@54006800 {
  28                         compatible = "socionext,uniphier-uart";
  29                         status = "disabled";
  30                         reg = <0x54006800 0x40>;
  31                         interrupts = <0 33 4>;
  32                         pinctrl-names = "default";
  33                         pinctrl-0 = <&pinctrl_uart0>;
  34                         clocks = <&uart_clk>;
  35                 };
  36
  37                 serial1: serial@54006900 {
  38                         compatible = "socionext,uniphier-uart";
  39                         status = "disabled";
  40                         reg = <0x54006900 0x40>;
  41                         interrupts = <0 35 4>;
  42                         pinctrl-names = "default";
  43                         pinctrl-0 = <&pinctrl_uart1>;
  44                         clocks = <&uart_clk>;
  45                 };
  46
  47                 serial2: serial@54006a00 {
  48                         compatible = "socionext,uniphier-uart";
  49                         status = "disabled";
  50                         reg = <0x54006a00 0x40>;
  51                         interrupts = <0 37 4>;
  52                         pinctrl-names = "default";
  53                         pinctrl-0 = <&pinctrl_uart2>;
  54                         clocks = <&uart_clk>;
  55                 };
  56
  57                 serial3: serial@54006b00 {
  58                         compatible = "socionext,uniphier-uart";
  59                         status = "disabled";
  60                         reg = <0x54006b00 0x40>;
  61                         interrupts = <0 177 4>;
  62                         pinctrl-names = "default";
  63                         pinctrl-0 = <&pinctrl_uart3>;
  64                         clocks = <&uart_clk>;
  65                 };
  66
  67                 system_bus: system-bus@58c00000 {
  68                         compatible = "socionext,uniphier-system-bus";
  69                         status = "disabled";
  70                         reg = <0x58c00000 0x400>;
  71                         #address-cells = <2>;
  72                         #size-cells = <1>;
  73                         pinctrl-names = "default";
  74                         pinctrl-0 = <&pinctrl_system_bus>;
  75                 };
  76
  77                 smpctrl@59800000 {
  78                         compatible = "socionext,uniphier-smpctrl";
  79                         reg = <0x59801000 0x400>;
  80                 };
  81
  82                 mio: mioctrl@59810000 {
  83                         /* specify compatible in each SoC DTSI */
  84                         reg = <0x59810000 0x800>;
  85                         #clock-cells = <1>;
  86                 };
  87
  88                 peri: perictrl@59820000 {
  89                         /* specify compatible in each SoC DTSI */
  90                         reg = <0x59820000 0x200>;
  91                         #clock-cells = <1>;
  92                 };
  93
  94                 timer@60000200 {
  95                         compatible = "arm,cortex-a9-global-timer";
  96                         reg = <0x60000200 0x20>;
  97                         interrupts = <1 11 0x104>;
  98                         clocks = <&arm_timer_clk>;
  99                 };
 100
 101                 timer@60000600 {
 102                         compatible = "arm,cortex-a9-twd-timer";
 103                         reg = <0x60000600 0x20>;
 104                         interrupts = <1 13 0x104>;
 105                         clocks = <&arm_timer_clk>;
 106                 };
 107
 108                 intc: interrupt-controller@60001000 {
 109                         compatible = "arm,cortex-a9-gic";
 110                         reg = <0x60001000 0x1000>,
 111                               <0x60000100 0x100>;
 112                         #interrupt-cells = <3>;
 113                         interrupt-controller;
 114                 };
 115
 116                 soc-glue@5f800000 {
 117                         compatible = "simple-mfd", "syscon";
 118                         reg = <0x5f800000 0x2000>;
 119                         u-boot,dm-pre-reloc;
 120
 121                         pinctrl: pinctrl {
 122                                 /* specify compatible in each SoC DTSI */
 123                                 u-boot,dm-pre-reloc;
 124                         };
 125                 };
 126
 127                 sysctrl: sysctrl@61840000 {
 128                         /* specify compatible in each SoC DTSI */
 129                         reg = <0x61840000 0x4000>;
 130                         #clock-cells = <1>;
 131                         clock-names = "ref";
 132                         clocks = <&refclk>;
 133                 };
 134
 135                 nand: nand@68000000 {
 136                         compatible = "denali,denali-nand-dt";
 137                         status = "disabled";
 138                         reg-names = "nand_data", "denali_reg";
 139                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 140                         interrupts = <0 65 4>;
 141                         pinctrl-names = "default";
 142                         pinctrl-0 = <&pinctrl_nand>;
 143                 };
 144         };
 145 };
 146
 147 /include/ "uniphier-pinctrl.dtsi"