git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-common32.dtsi

   1 /*
   2  * Device Tree Source commonly used by UniPhier ARM SoCs
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+        X11
   8  */
   9
  10 /include/ "skeleton.dtsi"
  11
  12 / {
  13         psci {
  14                 compatible = "arm,psci-0.2";
  15                 method = "smc";
  16         };
  17
  18         clocks {
  19                 refclk: ref {
  20                         #clock-cells = <0>;
  21                         compatible = "fixed-clock";
  22                 };
  23         };
  24
  25         soc: soc {
  26                 compatible = "simple-bus";
  27                 #address-cells = <1>;
  28                 #size-cells = <1>;
  29                 ranges;
  30                 interrupt-parent = <&intc>;
  31                 u-boot,dm-pre-reloc;
  32
  33                 serial0: serial@54006800 {
  34                         compatible = "socionext,uniphier-uart";
  35                         status = "disabled";
  36                         reg = <0x54006800 0x40>;
  37                         interrupts = <0 33 4>;
  38                         pinctrl-names = "default";
  39                         pinctrl-0 = <&pinctrl_uart0>;
  40                         clocks = <&peri_clk 0>;
  41                 };
  42
  43                 serial1: serial@54006900 {
  44                         compatible = "socionext,uniphier-uart";
  45                         status = "disabled";
  46                         reg = <0x54006900 0x40>;
  47                         interrupts = <0 35 4>;
  48                         pinctrl-names = "default";
  49                         pinctrl-0 = <&pinctrl_uart1>;
  50                         clocks = <&peri_clk 1>;
  51                 };
  52
  53                 serial2: serial@54006a00 {
  54                         compatible = "socionext,uniphier-uart";
  55                         status = "disabled";
  56                         reg = <0x54006a00 0x40>;
  57                         interrupts = <0 37 4>;
  58                         pinctrl-names = "default";
  59                         pinctrl-0 = <&pinctrl_uart2>;
  60                         clocks = <&peri_clk 2>;
  61                 };
  62
  63                 serial3: serial@54006b00 {
  64                         compatible = "socionext,uniphier-uart";
  65                         status = "disabled";
  66                         reg = <0x54006b00 0x40>;
  67                         interrupts = <0 177 4>;
  68                         pinctrl-names = "default";
  69                         pinctrl-0 = <&pinctrl_uart3>;
  70                         clocks = <&peri_clk 3>;
  71                 };
  72
  73                 system_bus: system-bus@58c00000 {
  74                         compatible = "socionext,uniphier-system-bus";
  75                         status = "disabled";
  76                         reg = <0x58c00000 0x400>;
  77                         #address-cells = <2>;
  78                         #size-cells = <1>;
  79                         pinctrl-names = "default";
  80                         pinctrl-0 = <&pinctrl_system_bus>;
  81                 };
  82
  83                 smpctrl@59800000 {
  84                         compatible = "socionext,uniphier-smpctrl";
  85                         reg = <0x59801000 0x400>;
  86                 };
  87
  88                 mioctrl@59810000 {
  89                         compatible = "socionext,uniphier-mioctrl",
  90                                      "simple-mfd", "syscon";
  91                         reg = <0x59810000 0x800>;
  92                         u-boot,dm-pre-reloc;
  93
  94                         mio_clk: clock {
  95                                 #clock-cells = <1>;
  96                         };
  97
  98                         mio_rst: reset {
  99                                 #reset-cells = <1>;
 100                         };
 101                 };
 102
 103                 perictrl@59820000 {
 104                         compatible = "socionext,uniphier-perictrl",
 105                                      "simple-mfd", "syscon";
 106                         reg = <0x59820000 0x200>;
 107
 108                         peri_clk: clock {
 109                                 #clock-cells = <1>;
 110                         };
 111
 112                         peri_rst: reset {
 113                                 #reset-cells = <1>;
 114                         };
 115                 };
 116
 117                 timer@60000200 {
 118                         compatible = "arm,cortex-a9-global-timer";
 119                         reg = <0x60000200 0x20>;
 120                         interrupts = <1 11 0x104>;
 121                         clocks = <&arm_timer_clk>;
 122                 };
 123
 124                 timer@60000600 {
 125                         compatible = "arm,cortex-a9-twd-timer";
 126                         reg = <0x60000600 0x20>;
 127                         interrupts = <1 13 0x104>;
 128                         clocks = <&arm_timer_clk>;
 129                 };
 130
 131                 intc: interrupt-controller@60001000 {
 132                         compatible = "arm,cortex-a9-gic";
 133                         reg = <0x60001000 0x1000>,
 134                               <0x60000100 0x100>;
 135                         #interrupt-cells = <3>;
 136                         interrupt-controller;
 137                 };
 138
 139                 soc-glue@5f800000 {
 140                         compatible = "socionext,uniphier-soc-glue",
 141                                      "simple-mfd", "syscon";
 142                         reg = <0x5f800000 0x2000>;
 143                         u-boot,dm-pre-reloc;
 144
 145                         pinctrl: pinctrl {
 146                                 /* specify compatible in each SoC DTSI */
 147                                 u-boot,dm-pre-reloc;
 148                         };
 149                 };
 150
 151                 sysctrl@61840000 {
 152                         compatible = "socionext,uniphier-sysctrl",
 153                                      "simple-mfd", "syscon";
 154                         reg = <0x61840000 0x4000>;
 155
 156                         sys_clk: clock {
 157                                 #clock-cells = <1>;
 158                         };
 159
 160                         sys_rst: reset {
 161                                 #reset-cells = <1>;
 162                         };
 163                 };
 164
 165                 nand: nand@68000000 {
 166                         compatible = "denali,denali-nand-dt";
 167                         status = "disabled";
 168                         reg-names = "nand_data", "denali_reg";
 169                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 170                         interrupts = <0 65 4>;
 171                         pinctrl-names = "default";
 172                         pinctrl-0 = <&pinctrl_nand>;
 173                 };
 174         };
 175 };
 176
 177 /include/ "uniphier-pinctrl.dtsi"