2 * Device Tree Source for UniPhier LD11 SoC
4 * Copyright (C) 2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /memreserve/ 0x80000000 0x02000000;
13 compatible = "socionext,uniphier-ld11";
16 interrupt-parent = <&gic>;
35 compatible = "arm,cortex-a53", "arm,armv8";
37 clocks = <&sys_clk 33>;
38 enable-method = "psci";
39 operating-points-v2 = <&cluster0_opp>;
44 compatible = "arm,cortex-a53", "arm,armv8";
46 clocks = <&sys_clk 33>;
47 enable-method = "psci";
48 operating-points-v2 = <&cluster0_opp>;
52 cluster0_opp: opp_table {
53 compatible = "operating-points-v2";
57 opp-hz = /bits/ 64 <245000000>;
58 clock-latency-ns = <300>;
61 opp-hz = /bits/ 64 <250000000>;
62 clock-latency-ns = <300>;
65 opp-hz = /bits/ 64 <490000000>;
66 clock-latency-ns = <300>;
69 opp-hz = /bits/ 64 <500000000>;
70 clock-latency-ns = <300>;
73 opp-hz = /bits/ 64 <653334000>;
74 clock-latency-ns = <300>;
77 opp-hz = /bits/ 64 <666667000>;
78 clock-latency-ns = <300>;
81 opp-hz = /bits/ 64 <980000000>;
82 clock-latency-ns = <300>;
87 compatible = "arm,psci-1.0";
93 compatible = "fixed-clock";
95 clock-frequency = <25000000>;
100 compatible = "arm,armv8-timer";
101 interrupts = <1 13 4>,
108 compatible = "simple-bus";
109 #address-cells = <1>;
111 ranges = <0 0 0 0xffffffff>;
113 serial0: serial@54006800 {
114 compatible = "socionext,uniphier-uart";
116 reg = <0x54006800 0x40>;
117 interrupts = <0 33 4>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_uart0>;
120 clocks = <&peri_clk 0>;
121 clock-frequency = <58820000>;
124 serial1: serial@54006900 {
125 compatible = "socionext,uniphier-uart";
127 reg = <0x54006900 0x40>;
128 interrupts = <0 35 4>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_uart1>;
131 clocks = <&peri_clk 1>;
132 clock-frequency = <58820000>;
135 serial2: serial@54006a00 {
136 compatible = "socionext,uniphier-uart";
138 reg = <0x54006a00 0x40>;
139 interrupts = <0 37 4>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_uart2>;
142 clocks = <&peri_clk 2>;
143 clock-frequency = <58820000>;
146 serial3: serial@54006b00 {
147 compatible = "socionext,uniphier-uart";
149 reg = <0x54006b00 0x40>;
150 interrupts = <0 177 4>;
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_uart3>;
153 clocks = <&peri_clk 3>;
154 clock-frequency = <58820000>;
158 compatible = "socionext,uniphier-fi2c";
160 reg = <0x58780000 0x80>;
161 #address-cells = <1>;
163 interrupts = <0 41 4>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_i2c0>;
166 clocks = <&peri_clk 4>;
167 clock-frequency = <100000>;
171 compatible = "socionext,uniphier-fi2c";
173 reg = <0x58781000 0x80>;
174 #address-cells = <1>;
176 interrupts = <0 42 4>;
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_i2c1>;
179 clocks = <&peri_clk 5>;
180 clock-frequency = <100000>;
184 compatible = "socionext,uniphier-fi2c";
185 reg = <0x58782000 0x80>;
186 #address-cells = <1>;
188 interrupts = <0 43 4>;
189 clocks = <&peri_clk 6>;
190 clock-frequency = <400000>;
194 compatible = "socionext,uniphier-fi2c";
196 reg = <0x58783000 0x80>;
197 #address-cells = <1>;
199 interrupts = <0 44 4>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_i2c3>;
202 clocks = <&peri_clk 7>;
203 clock-frequency = <100000>;
207 compatible = "socionext,uniphier-fi2c";
209 reg = <0x58784000 0x80>;
210 #address-cells = <1>;
212 interrupts = <0 45 4>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_i2c4>;
215 clocks = <&peri_clk 8>;
216 clock-frequency = <100000>;
220 compatible = "socionext,uniphier-fi2c";
221 reg = <0x58785000 0x80>;
222 #address-cells = <1>;
224 interrupts = <0 25 4>;
225 clocks = <&peri_clk 9>;
226 clock-frequency = <400000>;
229 system_bus: system-bus@58c00000 {
230 compatible = "socionext,uniphier-system-bus";
232 reg = <0x58c00000 0x400>;
233 #address-cells = <2>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_system_bus>;
240 compatible = "socionext,uniphier-smpctrl";
241 reg = <0x59801000 0x400>;
245 compatible = "socionext,uniphier-ld11-sdctrl",
246 "simple-mfd", "syscon";
247 reg = <0x59810000 0x400>;
250 compatible = "socionext,uniphier-ld11-sd-reset";
256 compatible = "socionext,uniphier-ld11-perictrl",
257 "simple-mfd", "syscon";
258 reg = <0x59820000 0x200>;
261 compatible = "socionext,uniphier-ld11-peri-clock";
266 compatible = "socionext,uniphier-ld11-peri-reset";
271 emmc: sdhc@5a000000 {
272 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
273 reg = <0x5a000000 0x400>;
274 interrupts = <0 78 4>;
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_emmc_1v8>;
277 clocks = <&sys_clk 4>;
281 cdns,phy-input-delay-legacy = <4>;
282 cdns,phy-input-delay-mmc-highspeed = <2>;
283 cdns,phy-input-delay-mmc-ddr = <3>;
284 cdns,phy-dll-delay-sdclk = <21>;
285 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
289 compatible = "socionext,uniphier-ehci", "generic-ehci";
291 reg = <0x5a800100 0x100>;
292 interrupts = <0 243 4>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_usb0>;
295 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
296 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
301 compatible = "socionext,uniphier-ehci", "generic-ehci";
303 reg = <0x5a810100 0x100>;
304 interrupts = <0 244 4>;
305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_usb1>;
307 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
308 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
313 compatible = "socionext,uniphier-ehci", "generic-ehci";
315 reg = <0x5a820100 0x100>;
316 interrupts = <0 245 4>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_usb2>;
319 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
320 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
325 compatible = "socionext,uniphier-ld11-mioctrl",
326 "simple-mfd", "syscon";
327 reg = <0x5b3e0000 0x800>;
330 compatible = "socionext,uniphier-ld11-mio-clock";
335 compatible = "socionext,uniphier-ld11-mio-reset";
337 resets = <&sys_rst 7>;
342 compatible = "socionext,uniphier-ld11-soc-glue",
343 "simple-mfd", "syscon";
344 reg = <0x5f800000 0x2000>;
347 compatible = "socionext,uniphier-ld11-pinctrl";
352 compatible = "simple-mfd", "syscon";
353 reg = <0x5fc20000 0x200>;
356 gic: interrupt-controller@5fe00000 {
357 compatible = "arm,gic-v3";
358 reg = <0x5fe00000 0x10000>, /* GICD */
359 <0x5fe40000 0x80000>; /* GICR */
360 interrupt-controller;
361 #interrupt-cells = <3>;
362 interrupts = <1 9 4>;
366 compatible = "socionext,uniphier-ld11-sysctrl",
367 "simple-mfd", "syscon";
368 reg = <0x61840000 0x10000>;
371 compatible = "socionext,uniphier-ld11-clock";
376 compatible = "socionext,uniphier-ld11-reset";
381 nand: nand@68000000 {
382 compatible = "socionext,uniphier-denali-nand-v5b";
384 reg-names = "nand_data", "denali_reg";
385 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
386 interrupts = <0 65 4>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_nand>;
389 clocks = <&sys_clk 2>;
390 nand-ecc-strength = <8>;
395 /include/ "uniphier-pinctrl.dtsi"