2 * Device Tree Source for UniPhier LD11 SoC
4 * Copyright (C) 2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /memreserve/ 0x80000000 0x02000000;
13 compatible = "socionext,uniphier-ld11";
16 interrupt-parent = <&gic>;
35 compatible = "arm,cortex-a53", "arm,armv8";
37 clocks = <&sys_clk 33>;
38 enable-method = "psci";
39 operating-points-v2 = <&cluster0_opp>;
44 compatible = "arm,cortex-a53", "arm,armv8";
46 clocks = <&sys_clk 33>;
47 enable-method = "psci";
48 operating-points-v2 = <&cluster0_opp>;
52 cluster0_opp: opp_table {
53 compatible = "operating-points-v2";
57 opp-hz = /bits/ 64 <245000000>;
58 clock-latency-ns = <300>;
61 opp-hz = /bits/ 64 <250000000>;
62 clock-latency-ns = <300>;
65 opp-hz = /bits/ 64 <490000000>;
66 clock-latency-ns = <300>;
69 opp-hz = /bits/ 64 <500000000>;
70 clock-latency-ns = <300>;
73 opp-hz = /bits/ 64 <653334000>;
74 clock-latency-ns = <300>;
77 opp-hz = /bits/ 64 <666667000>;
78 clock-latency-ns = <300>;
81 opp-hz = /bits/ 64 <980000000>;
82 clock-latency-ns = <300>;
87 compatible = "arm,psci-1.0";
93 compatible = "fixed-clock";
95 clock-frequency = <25000000>;
100 compatible = "arm,armv8-timer";
101 interrupts = <1 13 4>,
108 compatible = "simple-bus";
109 #address-cells = <1>;
111 ranges = <0 0 0 0xffffffff>;
114 serial0: serial@54006800 {
115 compatible = "socionext,uniphier-uart";
117 reg = <0x54006800 0x40>;
118 interrupts = <0 33 4>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_uart0>;
121 clocks = <&peri_clk 0>;
122 clock-frequency = <58820000>;
125 serial1: serial@54006900 {
126 compatible = "socionext,uniphier-uart";
128 reg = <0x54006900 0x40>;
129 interrupts = <0 35 4>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_uart1>;
132 clocks = <&peri_clk 1>;
133 clock-frequency = <58820000>;
136 serial2: serial@54006a00 {
137 compatible = "socionext,uniphier-uart";
139 reg = <0x54006a00 0x40>;
140 interrupts = <0 37 4>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_uart2>;
143 clocks = <&peri_clk 2>;
144 clock-frequency = <58820000>;
147 serial3: serial@54006b00 {
148 compatible = "socionext,uniphier-uart";
150 reg = <0x54006b00 0x40>;
151 interrupts = <0 177 4>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_uart3>;
154 clocks = <&peri_clk 3>;
155 clock-frequency = <58820000>;
159 compatible = "socionext,uniphier-fi2c";
161 reg = <0x58780000 0x80>;
162 #address-cells = <1>;
164 interrupts = <0 41 4>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_i2c0>;
167 clocks = <&peri_clk 4>;
168 clock-frequency = <100000>;
172 compatible = "socionext,uniphier-fi2c";
174 reg = <0x58781000 0x80>;
175 #address-cells = <1>;
177 interrupts = <0 42 4>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_i2c1>;
180 clocks = <&peri_clk 5>;
181 clock-frequency = <100000>;
185 compatible = "socionext,uniphier-fi2c";
186 reg = <0x58782000 0x80>;
187 #address-cells = <1>;
189 interrupts = <0 43 4>;
190 clocks = <&peri_clk 6>;
191 clock-frequency = <400000>;
195 compatible = "socionext,uniphier-fi2c";
197 reg = <0x58783000 0x80>;
198 #address-cells = <1>;
200 interrupts = <0 44 4>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_i2c3>;
203 clocks = <&peri_clk 7>;
204 clock-frequency = <100000>;
208 compatible = "socionext,uniphier-fi2c";
210 reg = <0x58784000 0x80>;
211 #address-cells = <1>;
213 interrupts = <0 45 4>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_i2c4>;
216 clocks = <&peri_clk 8>;
217 clock-frequency = <100000>;
221 compatible = "socionext,uniphier-fi2c";
222 reg = <0x58785000 0x80>;
223 #address-cells = <1>;
225 interrupts = <0 25 4>;
226 clocks = <&peri_clk 9>;
227 clock-frequency = <400000>;
230 system_bus: system-bus@58c00000 {
231 compatible = "socionext,uniphier-system-bus";
233 reg = <0x58c00000 0x400>;
234 #address-cells = <2>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_system_bus>;
241 compatible = "socionext,uniphier-smpctrl";
242 reg = <0x59801000 0x400>;
246 compatible = "socionext,uniphier-ld11-sdctrl",
247 "simple-mfd", "syscon";
248 reg = <0x59810000 0x400>;
251 compatible = "socionext,uniphier-ld11-sd-reset";
257 compatible = "socionext,uniphier-ld11-perictrl",
258 "simple-mfd", "syscon";
259 reg = <0x59820000 0x200>;
262 compatible = "socionext,uniphier-ld11-peri-clock";
267 compatible = "socionext,uniphier-ld11-peri-reset";
272 emmc: sdhc@5a000000 {
273 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
274 reg = <0x5a000000 0x400>;
275 interrupts = <0 78 4>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_emmc_1v8>;
278 clocks = <&sys_clk 4>;
282 cdns,phy-input-delay-legacy = <4>;
283 cdns,phy-input-delay-mmc-highspeed = <2>;
284 cdns,phy-input-delay-mmc-ddr = <3>;
285 cdns,phy-dll-delay-sdclk = <21>;
286 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
290 compatible = "socionext,uniphier-ehci", "generic-ehci";
292 reg = <0x5a800100 0x100>;
293 interrupts = <0 243 4>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_usb0>;
296 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
297 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
302 compatible = "socionext,uniphier-ehci", "generic-ehci";
304 reg = <0x5a810100 0x100>;
305 interrupts = <0 244 4>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_usb1>;
308 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
309 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
314 compatible = "socionext,uniphier-ehci", "generic-ehci";
316 reg = <0x5a820100 0x100>;
317 interrupts = <0 245 4>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_usb2>;
320 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
321 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
326 compatible = "socionext,uniphier-ld11-mioctrl",
327 "simple-mfd", "syscon";
328 reg = <0x5b3e0000 0x800>;
331 compatible = "socionext,uniphier-ld11-mio-clock";
336 compatible = "socionext,uniphier-ld11-mio-reset";
338 resets = <&sys_rst 7>;
343 compatible = "socionext,uniphier-ld11-soc-glue",
344 "simple-mfd", "syscon";
345 reg = <0x5f800000 0x2000>;
349 compatible = "socionext,uniphier-ld11-pinctrl";
355 compatible = "simple-mfd", "syscon";
356 reg = <0x5fc20000 0x200>;
359 gic: interrupt-controller@5fe00000 {
360 compatible = "arm,gic-v3";
361 reg = <0x5fe00000 0x10000>, /* GICD */
362 <0x5fe40000 0x80000>; /* GICR */
363 interrupt-controller;
364 #interrupt-cells = <3>;
365 interrupts = <1 9 4>;
369 compatible = "socionext,uniphier-ld11-sysctrl",
370 "simple-mfd", "syscon";
371 reg = <0x61840000 0x10000>;
374 compatible = "socionext,uniphier-ld11-clock";
379 compatible = "socionext,uniphier-ld11-reset";
384 nand: nand@68000000 {
385 compatible = "socionext,uniphier-denali-nand-v5b";
387 reg-names = "nand_data", "denali_reg";
388 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
389 interrupts = <0 65 4>;
390 pinctrl-names = "default";
391 pinctrl-0 = <&pinctrl_nand>;
392 clocks = <&sys_clk 2>;
393 nand-ecc-strength = <8>;
398 /include/ "uniphier-pinctrl.dtsi"