git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-ld20.dtsi

   1 /*
   2  * Device Tree Source for UniPhier LD20 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/gpio/uniphier-gpio.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 /memreserve/ 0x80000000 0x02000000;
  15
  16 / {
  17         compatible = "socionext,uniphier-ld20";
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20         interrupt-parent = <&gic>;
  21
  22         cpus {
  23                 #address-cells = <2>;
  24                 #size-cells = <0>;
  25
  26                 cpu-map {
  27                         cluster0 {
  28                                 core0 {
  29                                         cpu = <&cpu0>;
  30                                 };
  31                                 core1 {
  32                                         cpu = <&cpu1>;
  33                                 };
  34                         };
  35
  36                         cluster1 {
  37                                 core0 {
  38                                         cpu = <&cpu2>;
  39                                 };
  40                                 core1 {
  41                                         cpu = <&cpu3>;
  42                                 };
  43                         };
  44                 };
  45
  46                 cpu0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a72", "arm,armv8";
  49                         reg = <0 0x000>;
  50                         clocks = <&sys_clk 32>;
  51                         enable-method = "psci";
  52                         operating-points-v2 = <&cluster0_opp>;
  53                         #cooling-cells = <2>;
  54                 };
  55
  56                 cpu1: cpu@1 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a72", "arm,armv8";
  59                         reg = <0 0x001>;
  60                         clocks = <&sys_clk 32>;
  61                         enable-method = "psci";
  62                         operating-points-v2 = <&cluster0_opp>;
  63                 };
  64
  65                 cpu2: cpu@100 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         reg = <0 0x100>;
  69                         clocks = <&sys_clk 33>;
  70                         enable-method = "psci";
  71                         operating-points-v2 = <&cluster1_opp>;
  72                         #cooling-cells = <2>;
  73                 };
  74
  75                 cpu3: cpu@101 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a53", "arm,armv8";
  78                         reg = <0 0x101>;
  79                         clocks = <&sys_clk 33>;
  80                         enable-method = "psci";
  81                         operating-points-v2 = <&cluster1_opp>;
  82                 };
  83         };
  84
  85         cluster0_opp: opp-table0 {
  86                 compatible = "operating-points-v2";
  87                 opp-shared;
  88
  89                 opp-250000000 {
  90                         opp-hz = /bits/ 64 <250000000>;
  91                         clock-latency-ns = <300>;
  92                 };
  93                 opp-275000000 {
  94                         opp-hz = /bits/ 64 <275000000>;
  95                         clock-latency-ns = <300>;
  96                 };
  97                 opp-500000000 {
  98                         opp-hz = /bits/ 64 <500000000>;
  99                         clock-latency-ns = <300>;
 100                 };
 101                 opp-550000000 {
 102                         opp-hz = /bits/ 64 <550000000>;
 103                         clock-latency-ns = <300>;
 104                 };
 105                 opp-666667000 {
 106                         opp-hz = /bits/ 64 <666667000>;
 107                         clock-latency-ns = <300>;
 108                 };
 109                 opp-733334000 {
 110                         opp-hz = /bits/ 64 <733334000>;
 111                         clock-latency-ns = <300>;
 112                 };
 113                 opp-1000000000 {
 114                         opp-hz = /bits/ 64 <1000000000>;
 115                         clock-latency-ns = <300>;
 116                 };
 117                 opp-1100000000 {
 118                         opp-hz = /bits/ 64 <1100000000>;
 119                         clock-latency-ns = <300>;
 120                 };
 121         };
 122
 123         cluster1_opp: opp-table1 {
 124                 compatible = "operating-points-v2";
 125                 opp-shared;
 126
 127                 opp-250000000 {
 128                         opp-hz = /bits/ 64 <250000000>;
 129                         clock-latency-ns = <300>;
 130                 };
 131                 opp-275000000 {
 132                         opp-hz = /bits/ 64 <275000000>;
 133                         clock-latency-ns = <300>;
 134                 };
 135                 opp-500000000 {
 136                         opp-hz = /bits/ 64 <500000000>;
 137                         clock-latency-ns = <300>;
 138                 };
 139                 opp-550000000 {
 140                         opp-hz = /bits/ 64 <550000000>;
 141                         clock-latency-ns = <300>;
 142                 };
 143                 opp-666667000 {
 144                         opp-hz = /bits/ 64 <666667000>;
 145                         clock-latency-ns = <300>;
 146                 };
 147                 opp-733334000 {
 148                         opp-hz = /bits/ 64 <733334000>;
 149                         clock-latency-ns = <300>;
 150                 };
 151                 opp-1000000000 {
 152                         opp-hz = /bits/ 64 <1000000000>;
 153                         clock-latency-ns = <300>;
 154                 };
 155                 opp-1100000000 {
 156                         opp-hz = /bits/ 64 <1100000000>;
 157                         clock-latency-ns = <300>;
 158                 };
 159         };
 160
 161         psci {
 162                 compatible = "arm,psci-1.0";
 163                 method = "smc";
 164         };
 165
 166         clocks {
 167                 refclk: ref {
 168                         compatible = "fixed-clock";
 169                         #clock-cells = <0>;
 170                         clock-frequency = <25000000>;
 171                 };
 172         };
 173
 174         emmc_pwrseq: emmc-pwrseq {
 175                 compatible = "mmc-pwrseq-emmc";
 176                 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
 177         };
 178
 179         timer {
 180                 compatible = "arm,armv8-timer";
 181                 interrupts = <1 13 4>,
 182                              <1 14 4>,
 183                              <1 11 4>,
 184                              <1 10 4>;
 185         };
 186
 187         thermal-zones {
 188                 cpu-thermal {
 189                         polling-delay-passive = <250>;  /* 250ms */
 190                         polling-delay = <1000>;         /* 1000ms */
 191                         thermal-sensors = <&pvtctl>;
 192
 193                         trips {
 194                                 cpu_crit: cpu-crit {
 195                                         temperature = <110000>; /* 110C */
 196                                         hysteresis = <2000>;
 197                                         type = "critical";
 198                                 };
 199                                 cpu_alert: cpu-alert {
 200                                         temperature = <100000>; /* 100C */
 201                                         hysteresis = <2000>;
 202                                         type = "passive";
 203                                 };
 204                         };
 205
 206                         cooling-maps {
 207                                 map0 {
 208                                         trip = <&cpu_alert>;
 209                                         cooling-device = <&cpu0
 210                                             THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 211                                 };
 212                                 map1 {
 213                                         trip = <&cpu_alert>;
 214                                         cooling-device = <&cpu2
 215                                             THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 216                                 };
 217                         };
 218                 };
 219         };
 220
 221         soc@0 {
 222                 compatible = "simple-bus";
 223                 #address-cells = <1>;
 224                 #size-cells = <1>;
 225                 ranges = <0 0 0 0xffffffff>;
 226
 227                 serial0: serial@54006800 {
 228                         compatible = "socionext,uniphier-uart";
 229                         status = "disabled";
 230                         reg = <0x54006800 0x40>;
 231                         interrupts = <0 33 4>;
 232                         pinctrl-names = "default";
 233                         pinctrl-0 = <&pinctrl_uart0>;
 234                         clocks = <&peri_clk 0>;
 235                         clock-frequency = <58820000>;
 236                         resets = <&peri_rst 0>;
 237                 };
 238
 239                 serial1: serial@54006900 {
 240                         compatible = "socionext,uniphier-uart";
 241                         status = "disabled";
 242                         reg = <0x54006900 0x40>;
 243                         interrupts = <0 35 4>;
 244                         pinctrl-names = "default";
 245                         pinctrl-0 = <&pinctrl_uart1>;
 246                         clocks = <&peri_clk 1>;
 247                         clock-frequency = <58820000>;
 248                         resets = <&peri_rst 1>;
 249                 };
 250
 251                 serial2: serial@54006a00 {
 252                         compatible = "socionext,uniphier-uart";
 253                         status = "disabled";
 254                         reg = <0x54006a00 0x40>;
 255                         interrupts = <0 37 4>;
 256                         pinctrl-names = "default";
 257                         pinctrl-0 = <&pinctrl_uart2>;
 258                         clocks = <&peri_clk 2>;
 259                         clock-frequency = <58820000>;
 260                         resets = <&peri_rst 2>;
 261                 };
 262
 263                 serial3: serial@54006b00 {
 264                         compatible = "socionext,uniphier-uart";
 265                         status = "disabled";
 266                         reg = <0x54006b00 0x40>;
 267                         interrupts = <0 177 4>;
 268                         pinctrl-names = "default";
 269                         pinctrl-0 = <&pinctrl_uart3>;
 270                         clocks = <&peri_clk 3>;
 271                         clock-frequency = <58820000>;
 272                         resets = <&peri_rst 3>;
 273                 };
 274
 275                 gpio: gpio@55000000 {
 276                         compatible = "socionext,uniphier-gpio";
 277                         reg = <0x55000000 0x200>;
 278                         interrupt-parent = <&aidet>;
 279                         interrupt-controller;
 280                         #interrupt-cells = <2>;
 281                         gpio-controller;
 282                         #gpio-cells = <2>;
 283                         gpio-ranges = <&pinctrl 0 0 0>,
 284                                       <&pinctrl 96 0 0>,
 285                                       <&pinctrl 160 0 0>;
 286                         gpio-ranges-group-names = "gpio_range0",
 287                                                   "gpio_range1",
 288                                                   "gpio_range2";
 289                         ngpios = <205>;
 290                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
 291                                                      <21 217 3>;
 292                 };
 293
 294                 adamv@57920000 {
 295                         compatible = "socionext,uniphier-ld20-adamv",
 296                                      "simple-mfd", "syscon";
 297                         reg = <0x57920000 0x1000>;
 298
 299                         adamv_rst: reset {
 300                                 compatible = "socionext,uniphier-ld20-adamv-reset";
 301                                 #reset-cells = <1>;
 302                         };
 303                 };
 304
 305                 i2c0: i2c@58780000 {
 306                         compatible = "socionext,uniphier-fi2c";
 307                         status = "disabled";
 308                         reg = <0x58780000 0x80>;
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311                         interrupts = <0 41 4>;
 312                         pinctrl-names = "default";
 313                         pinctrl-0 = <&pinctrl_i2c0>;
 314                         clocks = <&peri_clk 4>;
 315                         resets = <&peri_rst 4>;
 316                         clock-frequency = <100000>;
 317                 };
 318
 319                 i2c1: i2c@58781000 {
 320                         compatible = "socionext,uniphier-fi2c";
 321                         status = "disabled";
 322                         reg = <0x58781000 0x80>;
 323                         #address-cells = <1>;
 324                         #size-cells = <0>;
 325                         interrupts = <0 42 4>;
 326                         pinctrl-names = "default";
 327                         pinctrl-0 = <&pinctrl_i2c1>;
 328                         clocks = <&peri_clk 5>;
 329                         resets = <&peri_rst 5>;
 330                         clock-frequency = <100000>;
 331                 };
 332
 333                 i2c2: i2c@58782000 {
 334                         compatible = "socionext,uniphier-fi2c";
 335                         reg = <0x58782000 0x80>;
 336                         #address-cells = <1>;
 337                         #size-cells = <0>;
 338                         interrupts = <0 43 4>;
 339                         clocks = <&peri_clk 6>;
 340                         resets = <&peri_rst 6>;
 341                         clock-frequency = <400000>;
 342                 };
 343
 344                 i2c3: i2c@58783000 {
 345                         compatible = "socionext,uniphier-fi2c";
 346                         status = "disabled";
 347                         reg = <0x58783000 0x80>;
 348                         #address-cells = <1>;
 349                         #size-cells = <0>;
 350                         interrupts = <0 44 4>;
 351                         pinctrl-names = "default";
 352                         pinctrl-0 = <&pinctrl_i2c3>;
 353                         clocks = <&peri_clk 7>;
 354                         resets = <&peri_rst 7>;
 355                         clock-frequency = <100000>;
 356                 };
 357
 358                 i2c4: i2c@58784000 {
 359                         compatible = "socionext,uniphier-fi2c";
 360                         status = "disabled";
 361                         reg = <0x58784000 0x80>;
 362                         #address-cells = <1>;
 363                         #size-cells = <0>;
 364                         interrupts = <0 45 4>;
 365                         pinctrl-names = "default";
 366                         pinctrl-0 = <&pinctrl_i2c4>;
 367                         clocks = <&peri_clk 8>;
 368                         resets = <&peri_rst 8>;
 369                         clock-frequency = <100000>;
 370                 };
 371
 372                 i2c5: i2c@58785000 {
 373                         compatible = "socionext,uniphier-fi2c";
 374                         reg = <0x58785000 0x80>;
 375                         #address-cells = <1>;
 376                         #size-cells = <0>;
 377                         interrupts = <0 25 4>;
 378                         clocks = <&peri_clk 9>;
 379                         resets = <&peri_rst 9>;
 380                         clock-frequency = <400000>;
 381                 };
 382
 383                 system_bus: system-bus@58c00000 {
 384                         compatible = "socionext,uniphier-system-bus";
 385                         status = "disabled";
 386                         reg = <0x58c00000 0x400>;
 387                         #address-cells = <2>;
 388                         #size-cells = <1>;
 389                         pinctrl-names = "default";
 390                         pinctrl-0 = <&pinctrl_system_bus>;
 391                 };
 392
 393                 smpctrl@59801000 {
 394                         compatible = "socionext,uniphier-smpctrl";
 395                         reg = <0x59801000 0x400>;
 396                 };
 397
 398                 sdctrl@59810000 {
 399                         compatible = "socionext,uniphier-ld20-sdctrl",
 400                                      "simple-mfd", "syscon";
 401                         reg = <0x59810000 0x400>;
 402
 403                         sd_clk: clock {
 404                                 compatible = "socionext,uniphier-ld20-sd-clock";
 405                                 #clock-cells = <1>;
 406                         };
 407
 408                         sd_rst: reset {
 409                                 compatible = "socionext,uniphier-ld20-sd-reset";
 410                                 #reset-cells = <1>;
 411                         };
 412                 };
 413
 414                 perictrl@59820000 {
 415                         compatible = "socionext,uniphier-ld20-perictrl",
 416                                      "simple-mfd", "syscon";
 417                         reg = <0x59820000 0x200>;
 418
 419                         peri_clk: clock {
 420                                 compatible = "socionext,uniphier-ld20-peri-clock";
 421                                 #clock-cells = <1>;
 422                         };
 423
 424                         peri_rst: reset {
 425                                 compatible = "socionext,uniphier-ld20-peri-reset";
 426                                 #reset-cells = <1>;
 427                         };
 428                 };
 429
 430                 emmc: sdhc@5a000000 {
 431                         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 432                         reg = <0x5a000000 0x400>;
 433                         interrupts = <0 78 4>;
 434                         pinctrl-names = "default";
 435                         pinctrl-0 = <&pinctrl_emmc_1v8>;
 436                         clocks = <&sys_clk 4>;
 437                         resets = <&sys_rst 4>;
 438                         bus-width = <8>;
 439                         mmc-ddr-1_8v;
 440                         mmc-hs200-1_8v;
 441                         mmc-pwrseq = <&emmc_pwrseq>;
 442                         cdns,phy-input-delay-legacy = <4>;
 443                         cdns,phy-input-delay-mmc-highspeed = <2>;
 444                         cdns,phy-input-delay-mmc-ddr = <3>;
 445                         cdns,phy-dll-delay-sdclk = <21>;
 446                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 447                 };
 448
 449                 sd: sdhc@5a400000 {
 450                         compatible = "socionext,uniphier-sdhc";
 451                         status = "disabled";
 452                         reg = <0x5a400000 0x800>;
 453                         interrupts = <0 76 4>;
 454                         pinctrl-names = "default";
 455                         pinctrl-0 = <&pinctrl_sd>;
 456                         clocks = <&sd_clk 0>;
 457                         reset-names = "host";
 458                         resets = <&sd_rst 0>;
 459                         bus-width = <4>;
 460                         cap-sd-highspeed;
 461                 };
 462
 463                 soc-glue@5f800000 {
 464                         compatible = "socionext,uniphier-ld20-soc-glue",
 465                                      "simple-mfd", "syscon";
 466                         reg = <0x5f800000 0x2000>;
 467
 468                         pinctrl: pinctrl {
 469                                 compatible = "socionext,uniphier-ld20-pinctrl";
 470                         };
 471                 };
 472
 473                 soc-glue@5f900000 {
 474                         compatible = "socionext,uniphier-ld20-soc-glue-debug",
 475                                      "simple-mfd";
 476                         #address-cells = <1>;
 477                         #size-cells = <1>;
 478                         ranges = <0 0x5f900000 0x2000>;
 479
 480                         efuse@100 {
 481                                 compatible = "socionext,uniphier-efuse";
 482                                 reg = <0x100 0x28>;
 483                         };
 484
 485                         efuse@200 {
 486                                 compatible = "socionext,uniphier-efuse";
 487                                 reg = <0x200 0x68>;
 488                         };
 489                 };
 490
 491                 aidet: aidet@5fc20000 {
 492                         compatible = "socionext,uniphier-ld20-aidet";
 493                         reg = <0x5fc20000 0x200>;
 494                         interrupt-controller;
 495                         #interrupt-cells = <2>;
 496                 };
 497
 498                 gic: interrupt-controller@5fe00000 {
 499                         compatible = "arm,gic-v3";
 500                         reg = <0x5fe00000 0x10000>,     /* GICD */
 501                               <0x5fe80000 0x80000>;     /* GICR */
 502                         interrupt-controller;
 503                         #interrupt-cells = <3>;
 504                         interrupts = <1 9 4>;
 505                 };
 506
 507                 sysctrl@61840000 {
 508                         compatible = "socionext,uniphier-ld20-sysctrl",
 509                                      "simple-mfd", "syscon";
 510                         reg = <0x61840000 0x10000>;
 511
 512                         sys_clk: clock {
 513                                 compatible = "socionext,uniphier-ld20-clock";
 514                                 #clock-cells = <1>;
 515                         };
 516
 517                         sys_rst: reset {
 518                                 compatible = "socionext,uniphier-ld20-reset";
 519                                 #reset-cells = <1>;
 520                         };
 521
 522                         watchdog {
 523                                 compatible = "socionext,uniphier-wdt";
 524                         };
 525
 526                         pvtctl: pvtctl {
 527                                 compatible = "socionext,uniphier-ld20-thermal";
 528                                 interrupts = <0 3 4>;
 529                                 #thermal-sensor-cells = <0>;
 530                                 socionext,tmod-calibration = <0x0f22 0x68ee>;
 531                         };
 532                 };
 533
 534                 usb: usb@65b00000 {
 535                         compatible = "socionext,uniphier-ld20-dwc3";
 536                         reg = <0x65b00000 0x1000>;
 537                         #address-cells = <1>;
 538                         #size-cells = <1>;
 539                         ranges;
 540                         pinctrl-names = "default";
 541                         pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
 542                                     <&pinctrl_usb2>, <&pinctrl_usb3>;
 543                         dwc3@65a00000 {
 544                                 compatible = "snps,dwc3";
 545                                 reg = <0x65a00000 0x10000>;
 546                                 interrupts = <0 134 4>;
 547                                 dr_mode = "host";
 548                                 tx-fifo-resize;
 549                         };
 550                 };
 551
 552                 nand: nand@68000000 {
 553                         compatible = "socionext,uniphier-denali-nand-v5b";
 554                         status = "disabled";
 555                         reg-names = "nand_data", "denali_reg";
 556                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 557                         interrupts = <0 65 4>;
 558                         pinctrl-names = "default";
 559                         pinctrl-0 = <&pinctrl_nand>;
 560                         clocks = <&sys_clk 2>;
 561                         resets = <&sys_rst 2>;
 562                 };
 563         };
 564 };
 565
 566 #include "uniphier-pinctrl.dtsi"