1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD20 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
12 /memreserve/ 0x80000000 0x02000000;
15 compatible = "socionext,uniphier-ld20";
18 interrupt-parent = <&gic>;
46 compatible = "arm,cortex-a72", "arm,armv8";
48 clocks = <&sys_clk 32>;
49 enable-method = "psci";
50 operating-points-v2 = <&cluster0_opp>;
56 compatible = "arm,cortex-a72", "arm,armv8";
58 clocks = <&sys_clk 32>;
59 enable-method = "psci";
60 operating-points-v2 = <&cluster0_opp>;
65 compatible = "arm,cortex-a53", "arm,armv8";
67 clocks = <&sys_clk 33>;
68 enable-method = "psci";
69 operating-points-v2 = <&cluster1_opp>;
75 compatible = "arm,cortex-a53", "arm,armv8";
77 clocks = <&sys_clk 33>;
78 enable-method = "psci";
79 operating-points-v2 = <&cluster1_opp>;
83 cluster0_opp: opp-table0 {
84 compatible = "operating-points-v2";
88 opp-hz = /bits/ 64 <250000000>;
89 clock-latency-ns = <300>;
92 opp-hz = /bits/ 64 <275000000>;
93 clock-latency-ns = <300>;
96 opp-hz = /bits/ 64 <500000000>;
97 clock-latency-ns = <300>;
100 opp-hz = /bits/ 64 <550000000>;
101 clock-latency-ns = <300>;
104 opp-hz = /bits/ 64 <666667000>;
105 clock-latency-ns = <300>;
108 opp-hz = /bits/ 64 <733334000>;
109 clock-latency-ns = <300>;
112 opp-hz = /bits/ 64 <1000000000>;
113 clock-latency-ns = <300>;
116 opp-hz = /bits/ 64 <1100000000>;
117 clock-latency-ns = <300>;
121 cluster1_opp: opp-table1 {
122 compatible = "operating-points-v2";
126 opp-hz = /bits/ 64 <250000000>;
127 clock-latency-ns = <300>;
130 opp-hz = /bits/ 64 <275000000>;
131 clock-latency-ns = <300>;
134 opp-hz = /bits/ 64 <500000000>;
135 clock-latency-ns = <300>;
138 opp-hz = /bits/ 64 <550000000>;
139 clock-latency-ns = <300>;
142 opp-hz = /bits/ 64 <666667000>;
143 clock-latency-ns = <300>;
146 opp-hz = /bits/ 64 <733334000>;
147 clock-latency-ns = <300>;
150 opp-hz = /bits/ 64 <1000000000>;
151 clock-latency-ns = <300>;
154 opp-hz = /bits/ 64 <1100000000>;
155 clock-latency-ns = <300>;
160 compatible = "arm,psci-1.0";
166 compatible = "fixed-clock";
168 clock-frequency = <25000000>;
172 emmc_pwrseq: emmc-pwrseq {
173 compatible = "mmc-pwrseq-emmc";
174 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
178 compatible = "arm,armv8-timer";
179 interrupts = <1 13 4>,
187 polling-delay-passive = <250>; /* 250ms */
188 polling-delay = <1000>; /* 1000ms */
189 thermal-sensors = <&pvtctl>;
193 temperature = <110000>; /* 110C */
197 cpu_alert: cpu-alert {
198 temperature = <100000>; /* 100C */
207 cooling-device = <&cpu0
208 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
212 cooling-device = <&cpu2
213 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
220 compatible = "simple-bus";
221 #address-cells = <1>;
223 ranges = <0 0 0 0xffffffff>;
225 serial0: serial@54006800 {
226 compatible = "socionext,uniphier-uart";
228 reg = <0x54006800 0x40>;
229 interrupts = <0 33 4>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_uart0>;
232 clocks = <&peri_clk 0>;
233 clock-frequency = <58820000>;
234 resets = <&peri_rst 0>;
237 serial1: serial@54006900 {
238 compatible = "socionext,uniphier-uart";
240 reg = <0x54006900 0x40>;
241 interrupts = <0 35 4>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_uart1>;
244 clocks = <&peri_clk 1>;
245 clock-frequency = <58820000>;
246 resets = <&peri_rst 1>;
249 serial2: serial@54006a00 {
250 compatible = "socionext,uniphier-uart";
252 reg = <0x54006a00 0x40>;
253 interrupts = <0 37 4>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_uart2>;
256 clocks = <&peri_clk 2>;
257 clock-frequency = <58820000>;
258 resets = <&peri_rst 2>;
261 serial3: serial@54006b00 {
262 compatible = "socionext,uniphier-uart";
264 reg = <0x54006b00 0x40>;
265 interrupts = <0 177 4>;
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_uart3>;
268 clocks = <&peri_clk 3>;
269 clock-frequency = <58820000>;
270 resets = <&peri_rst 3>;
273 gpio: gpio@55000000 {
274 compatible = "socionext,uniphier-gpio";
275 reg = <0x55000000 0x200>;
276 interrupt-parent = <&aidet>;
277 interrupt-controller;
278 #interrupt-cells = <2>;
281 gpio-ranges = <&pinctrl 0 0 0>,
284 gpio-ranges-group-names = "gpio_range0",
288 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
293 compatible = "socionext,uniphier-ld20-aio";
294 reg = <0x56000000 0x80000>;
295 interrupts = <0 144 4>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_aout1>,
300 clocks = <&sys_clk 40>;
302 resets = <&sys_rst 40>;
303 #sound-dai-cells = <1>;
304 socionext,syscon = <&soc_glue>;
312 i2s_pcmin2: endpoint {
319 remote-endpoint = <&evea_line>;
324 i2s_hpcmout1: endpoint {
331 remote-endpoint = <&evea_hp>;
335 spdif_port0: port@5 {
336 spdif_hiecout1: endpoint {
341 i2s_epcmout2: endpoint {
346 i2s_epcmout3: endpoint {
350 comp_spdif_port0: port@8 {
351 comp_spdif_hiecout1: endpoint {
357 compatible = "socionext,uniphier-evea";
358 reg = <0x57900000 0x1000>;
359 clock-names = "evea", "exiv";
360 clocks = <&sys_clk 41>, <&sys_clk 42>;
361 reset-names = "evea", "exiv", "adamv";
362 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
363 #sound-dai-cells = <1>;
366 evea_line: endpoint {
367 remote-endpoint = <&i2s_line>;
373 remote-endpoint = <&i2s_hp>;
379 compatible = "socionext,uniphier-ld20-adamv",
380 "simple-mfd", "syscon";
381 reg = <0x57920000 0x1000>;
384 compatible = "socionext,uniphier-ld20-adamv-reset";
390 compatible = "socionext,uniphier-fi2c";
392 reg = <0x58780000 0x80>;
393 #address-cells = <1>;
395 interrupts = <0 41 4>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&pinctrl_i2c0>;
398 clocks = <&peri_clk 4>;
399 resets = <&peri_rst 4>;
400 clock-frequency = <100000>;
404 compatible = "socionext,uniphier-fi2c";
406 reg = <0x58781000 0x80>;
407 #address-cells = <1>;
409 interrupts = <0 42 4>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&pinctrl_i2c1>;
412 clocks = <&peri_clk 5>;
413 resets = <&peri_rst 5>;
414 clock-frequency = <100000>;
418 compatible = "socionext,uniphier-fi2c";
419 reg = <0x58782000 0x80>;
420 #address-cells = <1>;
422 interrupts = <0 43 4>;
423 clocks = <&peri_clk 6>;
424 resets = <&peri_rst 6>;
425 clock-frequency = <400000>;
429 compatible = "socionext,uniphier-fi2c";
431 reg = <0x58783000 0x80>;
432 #address-cells = <1>;
434 interrupts = <0 44 4>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&pinctrl_i2c3>;
437 clocks = <&peri_clk 7>;
438 resets = <&peri_rst 7>;
439 clock-frequency = <100000>;
443 compatible = "socionext,uniphier-fi2c";
445 reg = <0x58784000 0x80>;
446 #address-cells = <1>;
448 interrupts = <0 45 4>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_i2c4>;
451 clocks = <&peri_clk 8>;
452 resets = <&peri_rst 8>;
453 clock-frequency = <100000>;
457 compatible = "socionext,uniphier-fi2c";
458 reg = <0x58785000 0x80>;
459 #address-cells = <1>;
461 interrupts = <0 25 4>;
462 clocks = <&peri_clk 9>;
463 resets = <&peri_rst 9>;
464 clock-frequency = <400000>;
467 system_bus: system-bus@58c00000 {
468 compatible = "socionext,uniphier-system-bus";
470 reg = <0x58c00000 0x400>;
471 #address-cells = <2>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&pinctrl_system_bus>;
478 compatible = "socionext,uniphier-smpctrl";
479 reg = <0x59801000 0x400>;
483 compatible = "socionext,uniphier-ld20-sdctrl",
484 "simple-mfd", "syscon";
485 reg = <0x59810000 0x400>;
488 compatible = "socionext,uniphier-ld20-sd-clock";
493 compatible = "socionext,uniphier-ld20-sd-reset";
499 compatible = "socionext,uniphier-ld20-perictrl",
500 "simple-mfd", "syscon";
501 reg = <0x59820000 0x200>;
504 compatible = "socionext,uniphier-ld20-peri-clock";
509 compatible = "socionext,uniphier-ld20-peri-reset";
514 emmc: sdhc@5a000000 {
515 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
516 reg = <0x5a000000 0x400>;
517 interrupts = <0 78 4>;
518 pinctrl-names = "default";
519 pinctrl-0 = <&pinctrl_emmc_1v8>;
520 clocks = <&sys_clk 4>;
521 resets = <&sys_rst 4>;
525 mmc-pwrseq = <&emmc_pwrseq>;
526 cdns,phy-input-delay-legacy = <4>;
527 cdns,phy-input-delay-mmc-highspeed = <2>;
528 cdns,phy-input-delay-mmc-ddr = <3>;
529 cdns,phy-dll-delay-sdclk = <21>;
530 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
534 compatible = "socionext,uniphier-sdhc";
536 reg = <0x5a400000 0x800>;
537 interrupts = <0 76 4>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_sd>;
540 clocks = <&sd_clk 0>;
541 reset-names = "host";
542 resets = <&sd_rst 0>;
547 soc_glue: soc-glue@5f800000 {
548 compatible = "socionext,uniphier-ld20-soc-glue",
549 "simple-mfd", "syscon";
550 reg = <0x5f800000 0x2000>;
553 compatible = "socionext,uniphier-ld20-pinctrl";
558 compatible = "socionext,uniphier-ld20-soc-glue-debug",
560 #address-cells = <1>;
562 ranges = <0 0x5f900000 0x2000>;
565 compatible = "socionext,uniphier-efuse";
570 compatible = "socionext,uniphier-efuse";
575 aidet: aidet@5fc20000 {
576 compatible = "socionext,uniphier-ld20-aidet";
577 reg = <0x5fc20000 0x200>;
578 interrupt-controller;
579 #interrupt-cells = <2>;
582 gic: interrupt-controller@5fe00000 {
583 compatible = "arm,gic-v3";
584 reg = <0x5fe00000 0x10000>, /* GICD */
585 <0x5fe80000 0x80000>; /* GICR */
586 interrupt-controller;
587 #interrupt-cells = <3>;
588 interrupts = <1 9 4>;
592 compatible = "socionext,uniphier-ld20-sysctrl",
593 "simple-mfd", "syscon";
594 reg = <0x61840000 0x10000>;
597 compatible = "socionext,uniphier-ld20-clock";
602 compatible = "socionext,uniphier-ld20-reset";
607 compatible = "socionext,uniphier-wdt";
611 compatible = "socionext,uniphier-ld20-thermal";
612 interrupts = <0 3 4>;
613 #thermal-sensor-cells = <0>;
614 socionext,tmod-calibration = <0x0f22 0x68ee>;
618 eth: ethernet@65000000 {
619 compatible = "socionext,uniphier-ld20-ave4";
621 reg = <0x65000000 0x8500>;
622 interrupts = <0 66 4>;
623 pinctrl-names = "default";
624 pinctrl-0 = <&pinctrl_ether_rgmii>;
625 clocks = <&sys_clk 6>;
626 resets = <&sys_rst 6>;
628 local-mac-address = [00 00 00 00 00 00];
631 #address-cells = <1>;
637 compatible = "socionext,uniphier-ld20-dwc3";
638 reg = <0x65b00000 0x1000>;
639 #address-cells = <1>;
642 pinctrl-names = "default";
643 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
644 <&pinctrl_usb2>, <&pinctrl_usb3>;
646 compatible = "snps,dwc3";
647 reg = <0x65a00000 0x10000>;
648 interrupts = <0 134 4>;
654 nand: nand@68000000 {
655 compatible = "socionext,uniphier-denali-nand-v5b";
657 reg-names = "nand_data", "denali_reg";
658 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
659 interrupts = <0 65 4>;
660 pinctrl-names = "default";
661 pinctrl-0 = <&pinctrl_nand>;
662 clocks = <&sys_clk 2>;
663 resets = <&sys_rst 2>;
668 #include "uniphier-pinctrl.dtsi"
671 drive-strength = <4>; /* default: 3.5mA */
675 drive-strength = <5>; /* 5mA */
680 drive-strength = <4>; /* default: 3.5mA */
684 drive-strength = <11>; /* 11mA */