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1 /*
2  * Device Tree Source for UniPhier LD20 SoC
3  *
4  * Copyright (C) 2015-2016 Socionext Inc.
5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+        X11
8  */
9
10 /memreserve/ 0x80000000 0x00080000;
11
12 / {
13         compatible = "socionext,uniphier-ld20";
14         #address-cells = <2>;
15         #size-cells = <2>;
16         interrupt-parent = <&gic>;
17
18         cpus {
19                 #address-cells = <2>;
20                 #size-cells = <0>;
21
22                 cpu-map {
23                         cluster0 {
24                                 core0 {
25                                         cpu = <&cpu0>;
26                                 };
27                                 core1 {
28                                         cpu = <&cpu1>;
29                                 };
30                         };
31
32                         cluster1 {
33                                 core0 {
34                                         cpu = <&cpu2>;
35                                 };
36                                 core1 {
37                                         cpu = <&cpu3>;
38                                 };
39                         };
40                 };
41
42                 cpu0: cpu@0 {
43                         device_type = "cpu";
44                         compatible = "arm,cortex-a72", "arm,armv8";
45                         reg = <0 0x000>;
46                         clocks = <&sys_clk 32>;
47                         enable-method = "psci";
48                         operating-points-v2 = <&cluster0_opp>;
49                 };
50
51                 cpu1: cpu@1 {
52                         device_type = "cpu";
53                         compatible = "arm,cortex-a72", "arm,armv8";
54                         reg = <0 0x001>;
55                         clocks = <&sys_clk 32>;
56                         enable-method = "psci";
57                         operating-points-v2 = <&cluster0_opp>;
58                 };
59
60                 cpu2: cpu@100 {
61                         device_type = "cpu";
62                         compatible = "arm,cortex-a53", "arm,armv8";
63                         reg = <0 0x100>;
64                         clocks = <&sys_clk 33>;
65                         enable-method = "psci";
66                         operating-points-v2 = <&cluster1_opp>;
67                 };
68
69                 cpu3: cpu@101 {
70                         device_type = "cpu";
71                         compatible = "arm,cortex-a53", "arm,armv8";
72                         reg = <0 0x101>;
73                         clocks = <&sys_clk 33>;
74                         enable-method = "psci";
75                         operating-points-v2 = <&cluster1_opp>;
76                 };
77         };
78
79         cluster0_opp: opp_table0 {
80                 compatible = "operating-points-v2";
81                 opp-shared;
82
83                 opp@250000000 {
84                         opp-hz = /bits/ 64 <250000000>;
85                         clock-latency-ns = <300>;
86                 };
87                 opp@275000000 {
88                         opp-hz = /bits/ 64 <275000000>;
89                         clock-latency-ns = <300>;
90                 };
91                 opp@500000000 {
92                         opp-hz = /bits/ 64 <500000000>;
93                         clock-latency-ns = <300>;
94                 };
95                 opp@550000000 {
96                         opp-hz = /bits/ 64 <550000000>;
97                         clock-latency-ns = <300>;
98                 };
99                 opp@666667000 {
100                         opp-hz = /bits/ 64 <666667000>;
101                         clock-latency-ns = <300>;
102                 };
103                 opp@733334000 {
104                         opp-hz = /bits/ 64 <733334000>;
105                         clock-latency-ns = <300>;
106                 };
107                 opp@1000000000 {
108                         opp-hz = /bits/ 64 <1000000000>;
109                         clock-latency-ns = <300>;
110                 };
111                 opp@1100000000 {
112                         opp-hz = /bits/ 64 <1100000000>;
113                         clock-latency-ns = <300>;
114                 };
115         };
116
117         cluster1_opp: opp_table1 {
118                 compatible = "operating-points-v2";
119                 opp-shared;
120
121                 opp@250000000 {
122                         opp-hz = /bits/ 64 <250000000>;
123                         clock-latency-ns = <300>;
124                 };
125                 opp@275000000 {
126                         opp-hz = /bits/ 64 <275000000>;
127                         clock-latency-ns = <300>;
128                 };
129                 opp@500000000 {
130                         opp-hz = /bits/ 64 <500000000>;
131                         clock-latency-ns = <300>;
132                 };
133                 opp@550000000 {
134                         opp-hz = /bits/ 64 <550000000>;
135                         clock-latency-ns = <300>;
136                 };
137                 opp@666667000 {
138                         opp-hz = /bits/ 64 <666667000>;
139                         clock-latency-ns = <300>;
140                 };
141                 opp@733334000 {
142                         opp-hz = /bits/ 64 <733334000>;
143                         clock-latency-ns = <300>;
144                 };
145                 opp@1000000000 {
146                         opp-hz = /bits/ 64 <1000000000>;
147                         clock-latency-ns = <300>;
148                 };
149                 opp@1100000000 {
150                         opp-hz = /bits/ 64 <1100000000>;
151                         clock-latency-ns = <300>;
152                 };
153         };
154
155         psci {
156                 compatible = "arm,psci-1.0";
157                 method = "smc";
158         };
159
160         clocks {
161                 refclk: ref {
162                         compatible = "fixed-clock";
163                         #clock-cells = <0>;
164                         clock-frequency = <25000000>;
165                 };
166         };
167
168         timer {
169                 compatible = "arm,armv8-timer";
170                 interrupts = <1 13 4>,
171                              <1 14 4>,
172                              <1 11 4>,
173                              <1 10 4>;
174         };
175
176         soc@0 {
177                 compatible = "simple-bus";
178                 #address-cells = <1>;
179                 #size-cells = <1>;
180                 ranges = <0 0 0 0xffffffff>;
181                 u-boot,dm-pre-reloc;
182
183                 serial0: serial@54006800 {
184                         compatible = "socionext,uniphier-uart";
185                         status = "disabled";
186                         reg = <0x54006800 0x40>;
187                         interrupts = <0 33 4>;
188                         pinctrl-names = "default";
189                         pinctrl-0 = <&pinctrl_uart0>;
190                         clocks = <&peri_clk 0>;
191                         clock-frequency = <58820000>;
192                 };
193
194                 serial1: serial@54006900 {
195                         compatible = "socionext,uniphier-uart";
196                         status = "disabled";
197                         reg = <0x54006900 0x40>;
198                         interrupts = <0 35 4>;
199                         pinctrl-names = "default";
200                         pinctrl-0 = <&pinctrl_uart1>;
201                         clocks = <&peri_clk 1>;
202                         clock-frequency = <58820000>;
203                 };
204
205                 serial2: serial@54006a00 {
206                         compatible = "socionext,uniphier-uart";
207                         status = "disabled";
208                         reg = <0x54006a00 0x40>;
209                         interrupts = <0 37 4>;
210                         pinctrl-names = "default";
211                         pinctrl-0 = <&pinctrl_uart2>;
212                         clocks = <&peri_clk 2>;
213                         clock-frequency = <58820000>;
214                 };
215
216                 serial3: serial@54006b00 {
217                         compatible = "socionext,uniphier-uart";
218                         status = "disabled";
219                         reg = <0x54006b00 0x40>;
220                         interrupts = <0 177 4>;
221                         pinctrl-names = "default";
222                         pinctrl-0 = <&pinctrl_uart3>;
223                         clocks = <&peri_clk 3>;
224                         clock-frequency = <58820000>;
225                 };
226
227                 i2c0: i2c@58780000 {
228                         compatible = "socionext,uniphier-fi2c";
229                         status = "disabled";
230                         reg = <0x58780000 0x80>;
231                         #address-cells = <1>;
232                         #size-cells = <0>;
233                         interrupts = <0 41 4>;
234                         pinctrl-names = "default";
235                         pinctrl-0 = <&pinctrl_i2c0>;
236                         clocks = <&peri_clk 4>;
237                         clock-frequency = <100000>;
238                 };
239
240                 i2c1: i2c@58781000 {
241                         compatible = "socionext,uniphier-fi2c";
242                         status = "disabled";
243                         reg = <0x58781000 0x80>;
244                         #address-cells = <1>;
245                         #size-cells = <0>;
246                         interrupts = <0 42 4>;
247                         pinctrl-names = "default";
248                         pinctrl-0 = <&pinctrl_i2c1>;
249                         clocks = <&peri_clk 5>;
250                         clock-frequency = <100000>;
251                 };
252
253                 i2c2: i2c@58782000 {
254                         compatible = "socionext,uniphier-fi2c";
255                         reg = <0x58782000 0x80>;
256                         #address-cells = <1>;
257                         #size-cells = <0>;
258                         interrupts = <0 43 4>;
259                         clocks = <&peri_clk 6>;
260                         clock-frequency = <400000>;
261                 };
262
263                 i2c3: i2c@58783000 {
264                         compatible = "socionext,uniphier-fi2c";
265                         status = "disabled";
266                         reg = <0x58783000 0x80>;
267                         #address-cells = <1>;
268                         #size-cells = <0>;
269                         interrupts = <0 44 4>;
270                         pinctrl-names = "default";
271                         pinctrl-0 = <&pinctrl_i2c3>;
272                         clocks = <&peri_clk 7>;
273                         clock-frequency = <100000>;
274                 };
275
276                 i2c4: i2c@58784000 {
277                         compatible = "socionext,uniphier-fi2c";
278                         status = "disabled";
279                         reg = <0x58784000 0x80>;
280                         #address-cells = <1>;
281                         #size-cells = <0>;
282                         interrupts = <0 45 4>;
283                         pinctrl-names = "default";
284                         pinctrl-0 = <&pinctrl_i2c4>;
285                         clocks = <&peri_clk 8>;
286                         clock-frequency = <100000>;
287                 };
288
289                 i2c5: i2c@58785000 {
290                         compatible = "socionext,uniphier-fi2c";
291                         reg = <0x58785000 0x80>;
292                         #address-cells = <1>;
293                         #size-cells = <0>;
294                         interrupts = <0 25 4>;
295                         clocks = <&peri_clk 9>;
296                         clock-frequency = <400000>;
297                 };
298
299                 system_bus: system-bus@58c00000 {
300                         compatible = "socionext,uniphier-system-bus";
301                         status = "disabled";
302                         reg = <0x58c00000 0x400>;
303                         #address-cells = <2>;
304                         #size-cells = <1>;
305                         pinctrl-names = "default";
306                         pinctrl-0 = <&pinctrl_system_bus>;
307                 };
308
309                 smpctrl@59800000 {
310                         compatible = "socionext,uniphier-smpctrl";
311                         reg = <0x59801000 0x400>;
312                 };
313
314                 sdctrl@59810000 {
315                         compatible = "socionext,uniphier-ld20-sdctrl",
316                                      "simple-mfd", "syscon";
317                         reg = <0x59810000 0x800>;
318
319                         sd_clk: clock {
320                                 compatible = "socionext,uniphier-ld20-sd-clock";
321                                 #clock-cells = <1>;
322                         };
323
324                         sd_rst: reset {
325                                 compatible = "socionext,uniphier-ld20-sd-reset";
326                                 #reset-cells = <1>;
327                         };
328                 };
329
330                 perictrl@59820000 {
331                         compatible = "socionext,uniphier-ld20-perictrl",
332                                      "simple-mfd", "syscon";
333                         reg = <0x59820000 0x200>;
334
335                         peri_clk: clock {
336                                 compatible = "socionext,uniphier-ld20-peri-clock";
337                                 #clock-cells = <1>;
338                         };
339
340                         peri_rst: reset {
341                                 compatible = "socionext,uniphier-ld20-peri-reset";
342                                 #reset-cells = <1>;
343                         };
344                 };
345
346                 emmc: sdhc@5a000000 {
347                         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
348                         reg = <0x5a000000 0x400>;
349                         interrupts = <0 78 4>;
350                         pinctrl-names = "default";
351                         pinctrl-0 = <&pinctrl_emmc_1v8>;
352                         clocks = <&sys_clk 4>;
353                         bus-width = <8>;
354                         mmc-ddr-1_8v;
355                         mmc-hs200-1_8v;
356                 };
357
358                 sd: sdhc@5a400000 {
359                         compatible = "socionext,uniphier-sdhc";
360                         status = "disabled";
361                         reg = <0x5a400000 0x800>;
362                         interrupts = <0 76 4>;
363                         pinctrl-names = "default";
364                         pinctrl-0 = <&pinctrl_sd>;
365                         clocks = <&sd_clk 0>;
366                         reset-names = "host";
367                         resets = <&sd_rst 0>;
368                         bus-width = <4>;
369                         cap-sd-highspeed;
370                 };
371
372                 soc-glue@5f800000 {
373                         compatible = "socionext,uniphier-ld20-soc-glue",
374                                      "simple-mfd", "syscon";
375                         reg = <0x5f800000 0x2000>;
376                         u-boot,dm-pre-reloc;
377
378                         pinctrl: pinctrl {
379                                 compatible = "socionext,uniphier-ld20-pinctrl";
380                                 u-boot,dm-pre-reloc;
381                         };
382                 };
383
384                 aidet@5fc20000 {
385                         compatible = "simple-mfd", "syscon";
386                         reg = <0x5fc20000 0x200>;
387                 };
388
389                 gic: interrupt-controller@5fe00000 {
390                         compatible = "arm,gic-v3";
391                         reg = <0x5fe00000 0x10000>,     /* GICD */
392                               <0x5fe80000 0x80000>;     /* GICR */
393                         interrupt-controller;
394                         #interrupt-cells = <3>;
395                         interrupts = <1 9 4>;
396                 };
397
398                 sysctrl@61840000 {
399                         compatible = "socionext,uniphier-ld20-sysctrl",
400                                      "simple-mfd", "syscon";
401                         reg = <0x61840000 0x10000>;
402
403                         sys_clk: clock {
404                                 compatible = "socionext,uniphier-ld20-clock";
405                                 #clock-cells = <1>;
406                         };
407
408                         sys_rst: reset {
409                                 compatible = "socionext,uniphier-ld20-reset";
410                                 #reset-cells = <1>;
411                         };
412                 };
413
414                 usb: usb@65b00000 {
415                         compatible = "socionext,uniphier-ld20-dwc3";
416                         reg = <0x65b00000 0x1000>;
417                         #address-cells = <1>;
418                         #size-cells = <1>;
419                         ranges;
420                         pinctrl-names = "default";
421                         pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
422                                     <&pinctrl_usb2>, <&pinctrl_usb3>;
423                         dwc3@65a00000 {
424                                 compatible = "snps,dwc3";
425                                 reg = <0x65a00000 0x10000>;
426                                 interrupts = <0 134 4>;
427                                 tx-fifo-resize;
428                         };
429                 };
430
431                 nand: nand@68000000 {
432                         compatible = "socionext,denali-nand-v5b";
433                         status = "disabled";
434                         reg-names = "nand_data", "denali_reg";
435                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
436                         interrupts = <0 65 4>;
437                         pinctrl-names = "default";
438                         pinctrl-0 = <&pinctrl_nand>;
439                         clocks = <&sys_clk 2>;
440                         nand-ecc-strength = <8>;
441                 };
442         };
443 };
444
445 /include/ "uniphier-pinctrl.dtsi"