1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD20 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
12 /memreserve/ 0x80000000 0x02000000;
15 compatible = "socionext,uniphier-ld20";
18 interrupt-parent = <&gic>;
46 compatible = "arm,cortex-a72", "arm,armv8";
48 clocks = <&sys_clk 32>;
49 enable-method = "psci";
50 operating-points-v2 = <&cluster0_opp>;
56 compatible = "arm,cortex-a72", "arm,armv8";
58 clocks = <&sys_clk 32>;
59 enable-method = "psci";
60 operating-points-v2 = <&cluster0_opp>;
65 compatible = "arm,cortex-a53", "arm,armv8";
67 clocks = <&sys_clk 33>;
68 enable-method = "psci";
69 operating-points-v2 = <&cluster1_opp>;
75 compatible = "arm,cortex-a53", "arm,armv8";
77 clocks = <&sys_clk 33>;
78 enable-method = "psci";
79 operating-points-v2 = <&cluster1_opp>;
83 cluster0_opp: opp-table0 {
84 compatible = "operating-points-v2";
88 opp-hz = /bits/ 64 <250000000>;
89 clock-latency-ns = <300>;
92 opp-hz = /bits/ 64 <275000000>;
93 clock-latency-ns = <300>;
96 opp-hz = /bits/ 64 <500000000>;
97 clock-latency-ns = <300>;
100 opp-hz = /bits/ 64 <550000000>;
101 clock-latency-ns = <300>;
104 opp-hz = /bits/ 64 <666667000>;
105 clock-latency-ns = <300>;
108 opp-hz = /bits/ 64 <733334000>;
109 clock-latency-ns = <300>;
112 opp-hz = /bits/ 64 <1000000000>;
113 clock-latency-ns = <300>;
116 opp-hz = /bits/ 64 <1100000000>;
117 clock-latency-ns = <300>;
121 cluster1_opp: opp-table1 {
122 compatible = "operating-points-v2";
126 opp-hz = /bits/ 64 <250000000>;
127 clock-latency-ns = <300>;
130 opp-hz = /bits/ 64 <275000000>;
131 clock-latency-ns = <300>;
134 opp-hz = /bits/ 64 <500000000>;
135 clock-latency-ns = <300>;
138 opp-hz = /bits/ 64 <550000000>;
139 clock-latency-ns = <300>;
142 opp-hz = /bits/ 64 <666667000>;
143 clock-latency-ns = <300>;
146 opp-hz = /bits/ 64 <733334000>;
147 clock-latency-ns = <300>;
150 opp-hz = /bits/ 64 <1000000000>;
151 clock-latency-ns = <300>;
154 opp-hz = /bits/ 64 <1100000000>;
155 clock-latency-ns = <300>;
160 compatible = "arm,psci-1.0";
166 compatible = "fixed-clock";
168 clock-frequency = <25000000>;
172 emmc_pwrseq: emmc-pwrseq {
173 compatible = "mmc-pwrseq-emmc";
174 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
178 compatible = "arm,armv8-timer";
179 interrupts = <1 13 4>,
187 polling-delay-passive = <250>; /* 250ms */
188 polling-delay = <1000>; /* 1000ms */
189 thermal-sensors = <&pvtctl>;
193 temperature = <110000>; /* 110C */
197 cpu_alert: cpu-alert {
198 temperature = <100000>; /* 100C */
207 cooling-device = <&cpu0
208 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
212 cooling-device = <&cpu2
213 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
220 compatible = "simple-bus";
221 #address-cells = <1>;
223 ranges = <0 0 0 0xffffffff>;
225 serial0: serial@54006800 {
226 compatible = "socionext,uniphier-uart";
228 reg = <0x54006800 0x40>;
229 interrupts = <0 33 4>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_uart0>;
232 clocks = <&peri_clk 0>;
233 resets = <&peri_rst 0>;
236 serial1: serial@54006900 {
237 compatible = "socionext,uniphier-uart";
239 reg = <0x54006900 0x40>;
240 interrupts = <0 35 4>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_uart1>;
243 clocks = <&peri_clk 1>;
244 resets = <&peri_rst 1>;
247 serial2: serial@54006a00 {
248 compatible = "socionext,uniphier-uart";
250 reg = <0x54006a00 0x40>;
251 interrupts = <0 37 4>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_uart2>;
254 clocks = <&peri_clk 2>;
255 resets = <&peri_rst 2>;
258 serial3: serial@54006b00 {
259 compatible = "socionext,uniphier-uart";
261 reg = <0x54006b00 0x40>;
262 interrupts = <0 177 4>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_uart3>;
265 clocks = <&peri_clk 3>;
266 resets = <&peri_rst 3>;
269 gpio: gpio@55000000 {
270 compatible = "socionext,uniphier-gpio";
271 reg = <0x55000000 0x200>;
272 interrupt-parent = <&aidet>;
273 interrupt-controller;
274 #interrupt-cells = <2>;
277 gpio-ranges = <&pinctrl 0 0 0>,
280 gpio-ranges-group-names = "gpio_range0",
284 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
289 compatible = "socionext,uniphier-ld20-aio";
290 reg = <0x56000000 0x80000>;
291 interrupts = <0 144 4>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_aout1>,
296 clocks = <&sys_clk 40>;
298 resets = <&sys_rst 40>;
299 #sound-dai-cells = <1>;
300 socionext,syscon = <&soc_glue>;
308 i2s_pcmin2: endpoint {
315 remote-endpoint = <&evea_line>;
320 i2s_hpcmout1: endpoint {
327 remote-endpoint = <&evea_hp>;
331 spdif_port0: port@5 {
332 spdif_hiecout1: endpoint {
337 i2s_epcmout2: endpoint {
342 i2s_epcmout3: endpoint {
346 comp_spdif_port0: port@8 {
347 comp_spdif_hiecout1: endpoint {
353 compatible = "socionext,uniphier-evea";
354 reg = <0x57900000 0x1000>;
355 clock-names = "evea", "exiv";
356 clocks = <&sys_clk 41>, <&sys_clk 42>;
357 reset-names = "evea", "exiv", "adamv";
358 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
359 #sound-dai-cells = <1>;
362 evea_line: endpoint {
363 remote-endpoint = <&i2s_line>;
369 remote-endpoint = <&i2s_hp>;
375 compatible = "socionext,uniphier-ld20-adamv",
376 "simple-mfd", "syscon";
377 reg = <0x57920000 0x1000>;
380 compatible = "socionext,uniphier-ld20-adamv-reset";
386 compatible = "socionext,uniphier-fi2c";
388 reg = <0x58780000 0x80>;
389 #address-cells = <1>;
391 interrupts = <0 41 4>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_i2c0>;
394 clocks = <&peri_clk 4>;
395 resets = <&peri_rst 4>;
396 clock-frequency = <100000>;
400 compatible = "socionext,uniphier-fi2c";
402 reg = <0x58781000 0x80>;
403 #address-cells = <1>;
405 interrupts = <0 42 4>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&pinctrl_i2c1>;
408 clocks = <&peri_clk 5>;
409 resets = <&peri_rst 5>;
410 clock-frequency = <100000>;
414 compatible = "socionext,uniphier-fi2c";
415 reg = <0x58782000 0x80>;
416 #address-cells = <1>;
418 interrupts = <0 43 4>;
419 clocks = <&peri_clk 6>;
420 resets = <&peri_rst 6>;
421 clock-frequency = <400000>;
425 compatible = "socionext,uniphier-fi2c";
427 reg = <0x58783000 0x80>;
428 #address-cells = <1>;
430 interrupts = <0 44 4>;
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_i2c3>;
433 clocks = <&peri_clk 7>;
434 resets = <&peri_rst 7>;
435 clock-frequency = <100000>;
439 compatible = "socionext,uniphier-fi2c";
441 reg = <0x58784000 0x80>;
442 #address-cells = <1>;
444 interrupts = <0 45 4>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&pinctrl_i2c4>;
447 clocks = <&peri_clk 8>;
448 resets = <&peri_rst 8>;
449 clock-frequency = <100000>;
453 compatible = "socionext,uniphier-fi2c";
454 reg = <0x58785000 0x80>;
455 #address-cells = <1>;
457 interrupts = <0 25 4>;
458 clocks = <&peri_clk 9>;
459 resets = <&peri_rst 9>;
460 clock-frequency = <400000>;
463 system_bus: system-bus@58c00000 {
464 compatible = "socionext,uniphier-system-bus";
466 reg = <0x58c00000 0x400>;
467 #address-cells = <2>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_system_bus>;
474 compatible = "socionext,uniphier-smpctrl";
475 reg = <0x59801000 0x400>;
479 compatible = "socionext,uniphier-ld20-sdctrl",
480 "simple-mfd", "syscon";
481 reg = <0x59810000 0x400>;
484 compatible = "socionext,uniphier-ld20-sd-clock";
489 compatible = "socionext,uniphier-ld20-sd-reset";
495 compatible = "socionext,uniphier-ld20-perictrl",
496 "simple-mfd", "syscon";
497 reg = <0x59820000 0x200>;
500 compatible = "socionext,uniphier-ld20-peri-clock";
505 compatible = "socionext,uniphier-ld20-peri-reset";
510 emmc: sdhc@5a000000 {
511 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
512 reg = <0x5a000000 0x400>;
513 interrupts = <0 78 4>;
514 pinctrl-names = "default";
515 pinctrl-0 = <&pinctrl_emmc_1v8>;
516 clocks = <&sys_clk 4>;
517 resets = <&sys_rst 4>;
521 mmc-pwrseq = <&emmc_pwrseq>;
522 cdns,phy-input-delay-legacy = <9>;
523 cdns,phy-input-delay-mmc-highspeed = <2>;
524 cdns,phy-input-delay-mmc-ddr = <3>;
525 cdns,phy-dll-delay-sdclk = <21>;
526 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
530 compatible = "socionext,uniphier-sdhc";
532 reg = <0x5a400000 0x800>;
533 interrupts = <0 76 4>;
534 pinctrl-names = "default";
535 pinctrl-0 = <&pinctrl_sd>;
536 clocks = <&sd_clk 0>;
537 reset-names = "host";
538 resets = <&sd_rst 0>;
543 soc_glue: soc-glue@5f800000 {
544 compatible = "socionext,uniphier-ld20-soc-glue",
545 "simple-mfd", "syscon";
546 reg = <0x5f800000 0x2000>;
549 compatible = "socionext,uniphier-ld20-pinctrl";
554 compatible = "socionext,uniphier-ld20-soc-glue-debug",
556 #address-cells = <1>;
558 ranges = <0 0x5f900000 0x2000>;
561 compatible = "socionext,uniphier-efuse";
566 compatible = "socionext,uniphier-efuse";
571 aidet: aidet@5fc20000 {
572 compatible = "socionext,uniphier-ld20-aidet";
573 reg = <0x5fc20000 0x200>;
574 interrupt-controller;
575 #interrupt-cells = <2>;
578 gic: interrupt-controller@5fe00000 {
579 compatible = "arm,gic-v3";
580 reg = <0x5fe00000 0x10000>, /* GICD */
581 <0x5fe80000 0x80000>; /* GICR */
582 interrupt-controller;
583 #interrupt-cells = <3>;
584 interrupts = <1 9 4>;
588 compatible = "socionext,uniphier-ld20-sysctrl",
589 "simple-mfd", "syscon";
590 reg = <0x61840000 0x10000>;
593 compatible = "socionext,uniphier-ld20-clock";
598 compatible = "socionext,uniphier-ld20-reset";
603 compatible = "socionext,uniphier-wdt";
607 compatible = "socionext,uniphier-ld20-thermal";
608 interrupts = <0 3 4>;
609 #thermal-sensor-cells = <0>;
610 socionext,tmod-calibration = <0x0f22 0x68ee>;
614 eth: ethernet@65000000 {
615 compatible = "socionext,uniphier-ld20-ave4";
617 reg = <0x65000000 0x8500>;
618 interrupts = <0 66 4>;
619 pinctrl-names = "default";
620 pinctrl-0 = <&pinctrl_ether_rgmii>;
621 clock-names = "ether";
622 clocks = <&sys_clk 6>;
623 reset-names = "ether";
624 resets = <&sys_rst 6>;
626 local-mac-address = [00 00 00 00 00 00];
627 socionext,syscon-phy-mode = <&soc_glue 0>;
630 #address-cells = <1>;
636 compatible = "socionext,uniphier-ld20-dwc3";
637 reg = <0x65b00000 0x1000>;
638 #address-cells = <1>;
641 pinctrl-names = "default";
642 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
643 <&pinctrl_usb2>, <&pinctrl_usb3>;
645 compatible = "snps,dwc3";
646 reg = <0x65a00000 0x10000>;
647 interrupts = <0 134 4>;
653 nand: nand@68000000 {
654 compatible = "socionext,uniphier-denali-nand-v5b";
656 reg-names = "nand_data", "denali_reg";
657 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
658 interrupts = <0 65 4>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&pinctrl_nand>;
661 clocks = <&sys_clk 2>;
662 resets = <&sys_rst 2>;
667 #include "uniphier-pinctrl.dtsi"
670 drive-strength = <4>; /* default: 3.5mA */
674 drive-strength = <5>; /* 5mA */
679 drive-strength = <4>; /* default: 3.5mA */
683 drive-strength = <11>; /* 11mA */