2 * Device Tree Source for UniPhier LD4 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 #include <dt-bindings/gpio/uniphier-gpio.h>
13 compatible = "socionext,uniphier-ld4";
23 compatible = "arm,cortex-a9";
25 enable-method = "psci";
26 next-level-cache = <&l2>;
31 compatible = "arm,psci-0.2";
37 compatible = "fixed-clock";
39 clock-frequency = <24576000>;
42 arm_timer_clk: arm-timer {
44 compatible = "fixed-clock";
45 clock-frequency = <50000000>;
50 compatible = "simple-bus";
54 interrupt-parent = <&intc>;
56 l2: l2-cache@500c0000 {
57 compatible = "socionext,uniphier-system-cache";
58 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
60 interrupts = <0 174 4>, <0 175 4>;
62 cache-size = <(512 * 1024)>;
64 cache-line-size = <128>;
68 serial0: serial@54006800 {
69 compatible = "socionext,uniphier-uart";
71 reg = <0x54006800 0x40>;
72 interrupts = <0 33 4>;
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_uart0>;
75 clocks = <&peri_clk 0>;
76 clock-frequency = <36864000>;
77 resets = <&peri_rst 0>;
80 serial1: serial@54006900 {
81 compatible = "socionext,uniphier-uart";
83 reg = <0x54006900 0x40>;
84 interrupts = <0 35 4>;
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_uart1>;
87 clocks = <&peri_clk 1>;
88 clock-frequency = <36864000>;
89 resets = <&peri_rst 1>;
92 serial2: serial@54006a00 {
93 compatible = "socionext,uniphier-uart";
95 reg = <0x54006a00 0x40>;
96 interrupts = <0 37 4>;
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_uart2>;
99 clocks = <&peri_clk 2>;
100 clock-frequency = <36864000>;
101 resets = <&peri_rst 2>;
104 serial3: serial@54006b00 {
105 compatible = "socionext,uniphier-uart";
107 reg = <0x54006b00 0x40>;
108 interrupts = <0 29 4>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_uart3>;
111 clocks = <&peri_clk 3>;
112 clock-frequency = <36864000>;
113 resets = <&peri_rst 3>;
116 gpio: gpio@55000000 {
117 compatible = "socionext,uniphier-gpio";
118 reg = <0x55000000 0x200>;
119 interrupt-parent = <&aidet>;
120 interrupt-controller;
121 #interrupt-cells = <2>;
124 gpio-ranges = <&pinctrl 0 0 0>;
125 gpio-ranges-group-names = "gpio_range";
127 socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
131 compatible = "socionext,uniphier-i2c";
133 reg = <0x58400000 0x40>;
134 #address-cells = <1>;
136 interrupts = <0 41 1>;
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_i2c0>;
139 clocks = <&peri_clk 4>;
140 resets = <&peri_rst 4>;
141 clock-frequency = <100000>;
145 compatible = "socionext,uniphier-i2c";
147 reg = <0x58480000 0x40>;
148 #address-cells = <1>;
150 interrupts = <0 42 1>;
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_i2c1>;
153 clocks = <&peri_clk 5>;
154 resets = <&peri_rst 5>;
155 clock-frequency = <100000>;
158 /* chip-internal connection for DMD */
160 compatible = "socionext,uniphier-i2c";
161 reg = <0x58500000 0x40>;
162 #address-cells = <1>;
164 interrupts = <0 43 1>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_i2c2>;
167 clocks = <&peri_clk 6>;
168 resets = <&peri_rst 6>;
169 clock-frequency = <400000>;
173 compatible = "socionext,uniphier-i2c";
175 reg = <0x58580000 0x40>;
176 #address-cells = <1>;
178 interrupts = <0 44 1>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_i2c3>;
181 clocks = <&peri_clk 7>;
182 resets = <&peri_rst 7>;
183 clock-frequency = <100000>;
186 system_bus: system-bus@58c00000 {
187 compatible = "socionext,uniphier-system-bus";
189 reg = <0x58c00000 0x400>;
190 #address-cells = <2>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_system_bus>;
197 compatible = "socionext,uniphier-smpctrl";
198 reg = <0x59801000 0x400>;
202 compatible = "socionext,uniphier-ld4-mioctrl",
203 "simple-mfd", "syscon";
204 reg = <0x59810000 0x800>;
207 compatible = "socionext,uniphier-ld4-mio-clock";
212 compatible = "socionext,uniphier-ld4-mio-reset";
218 compatible = "socionext,uniphier-ld4-perictrl",
219 "simple-mfd", "syscon";
220 reg = <0x59820000 0x200>;
223 compatible = "socionext,uniphier-ld4-peri-clock";
228 compatible = "socionext,uniphier-ld4-peri-reset";
234 compatible = "socionext,uniphier-sdhc";
236 reg = <0x5a400000 0x200>;
237 interrupts = <0 76 4>;
238 pinctrl-names = "default", "1.8v";
239 pinctrl-0 = <&pinctrl_sd>;
240 pinctrl-1 = <&pinctrl_sd_1v8>;
241 clocks = <&mio_clk 0>;
242 reset-names = "host", "bridge";
243 resets = <&mio_rst 0>, <&mio_rst 3>;
251 emmc: sdhc@5a500000 {
252 compatible = "socionext,uniphier-sdhc";
254 reg = <0x5a500000 0x200>;
255 interrupts = <0 78 4>;
256 pinctrl-names = "default", "1.8v";
257 pinctrl-0 = <&pinctrl_emmc>;
258 pinctrl-1 = <&pinctrl_emmc_1v8>;
259 clocks = <&mio_clk 1>;
260 reset-names = "host", "bridge";
261 resets = <&mio_rst 1>, <&mio_rst 4>;
269 compatible = "socionext,uniphier-ehci", "generic-ehci";
271 reg = <0x5a800100 0x100>;
272 interrupts = <0 80 4>;
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_usb0>;
275 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
277 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
279 has-transaction-translator;
283 compatible = "socionext,uniphier-ehci", "generic-ehci";
285 reg = <0x5a810100 0x100>;
286 interrupts = <0 81 4>;
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_usb1>;
289 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
291 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
293 has-transaction-translator;
297 compatible = "socionext,uniphier-ehci", "generic-ehci";
299 reg = <0x5a820100 0x100>;
300 interrupts = <0 82 4>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_usb2>;
303 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
305 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
307 has-transaction-translator;
311 compatible = "socionext,uniphier-ld4-soc-glue",
312 "simple-mfd", "syscon";
313 reg = <0x5f800000 0x2000>;
316 compatible = "socionext,uniphier-ld4-pinctrl";
321 compatible = "socionext,uniphier-ld4-soc-glue-debug",
323 #address-cells = <1>;
325 ranges = <0 0x5f900000 0x2000>;
328 compatible = "socionext,uniphier-efuse";
333 compatible = "socionext,uniphier-efuse";
339 compatible = "arm,cortex-a9-global-timer";
340 reg = <0x60000200 0x20>;
341 interrupts = <1 11 0x104>;
342 clocks = <&arm_timer_clk>;
346 compatible = "arm,cortex-a9-twd-timer";
347 reg = <0x60000600 0x20>;
348 interrupts = <1 13 0x104>;
349 clocks = <&arm_timer_clk>;
352 intc: interrupt-controller@60001000 {
353 compatible = "arm,cortex-a9-gic";
354 reg = <0x60001000 0x1000>,
356 #interrupt-cells = <3>;
357 interrupt-controller;
360 aidet: aidet@61830000 {
361 compatible = "socionext,uniphier-ld4-aidet";
362 reg = <0x61830000 0x200>;
363 interrupt-controller;
364 #interrupt-cells = <2>;
368 compatible = "socionext,uniphier-ld4-sysctrl",
369 "simple-mfd", "syscon";
370 reg = <0x61840000 0x10000>;
373 compatible = "socionext,uniphier-ld4-clock";
378 compatible = "socionext,uniphier-ld4-reset";
383 nand: nand@68000000 {
384 compatible = "socionext,uniphier-denali-nand-v5a";
386 reg-names = "nand_data", "denali_reg";
387 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
388 interrupts = <0 65 4>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&pinctrl_nand2cs>;
391 clocks = <&sys_clk 2>;
392 resets = <&sys_rst 2>;
397 #include "uniphier-pinctrl.dtsi"