git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-ld4.dtsi

   1 /*
   2  * Device Tree Source for UniPhier LD4 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 #include <dt-bindings/gpio/uniphier-gpio.h>
  11
  12 / {
  13         compatible = "socionext,uniphier-ld4";
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         reg = <0>;
  25                         enable-method = "psci";
  26                         next-level-cache = <&l2>;
  27                 };
  28         };
  29
  30         psci {
  31                 compatible = "arm,psci-0.2";
  32                 method = "smc";
  33         };
  34
  35         clocks {
  36                 refclk: ref {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                         clock-frequency = <24576000>;
  40                 };
  41
  42                 arm_timer_clk: arm-timer {
  43                         #clock-cells = <0>;
  44                         compatible = "fixed-clock";
  45                         clock-frequency = <50000000>;
  46                 };
  47         };
  48
  49         soc {
  50                 compatible = "simple-bus";
  51                 #address-cells = <1>;
  52                 #size-cells = <1>;
  53                 ranges;
  54                 interrupt-parent = <&intc>;
  55
  56                 l2: l2-cache@500c0000 {
  57                         compatible = "socionext,uniphier-system-cache";
  58                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  59                               <0x506c0000 0x400>;
  60                         interrupts = <0 174 4>, <0 175 4>;
  61                         cache-unified;
  62                         cache-size = <(512 * 1024)>;
  63                         cache-sets = <256>;
  64                         cache-line-size = <128>;
  65                         cache-level = <2>;
  66                 };
  67
  68                 serial0: serial@54006800 {
  69                         compatible = "socionext,uniphier-uart";
  70                         status = "disabled";
  71                         reg = <0x54006800 0x40>;
  72                         interrupts = <0 33 4>;
  73                         pinctrl-names = "default";
  74                         pinctrl-0 = <&pinctrl_uart0>;
  75                         clocks = <&peri_clk 0>;
  76                         clock-frequency = <36864000>;
  77                         resets = <&peri_rst 0>;
  78                 };
  79
  80                 serial1: serial@54006900 {
  81                         compatible = "socionext,uniphier-uart";
  82                         status = "disabled";
  83                         reg = <0x54006900 0x40>;
  84                         interrupts = <0 35 4>;
  85                         pinctrl-names = "default";
  86                         pinctrl-0 = <&pinctrl_uart1>;
  87                         clocks = <&peri_clk 1>;
  88                         clock-frequency = <36864000>;
  89                         resets = <&peri_rst 1>;
  90                 };
  91
  92                 serial2: serial@54006a00 {
  93                         compatible = "socionext,uniphier-uart";
  94                         status = "disabled";
  95                         reg = <0x54006a00 0x40>;
  96                         interrupts = <0 37 4>;
  97                         pinctrl-names = "default";
  98                         pinctrl-0 = <&pinctrl_uart2>;
  99                         clocks = <&peri_clk 2>;
 100                         clock-frequency = <36864000>;
 101                         resets = <&peri_rst 2>;
 102                 };
 103
 104                 serial3: serial@54006b00 {
 105                         compatible = "socionext,uniphier-uart";
 106                         status = "disabled";
 107                         reg = <0x54006b00 0x40>;
 108                         interrupts = <0 29 4>;
 109                         pinctrl-names = "default";
 110                         pinctrl-0 = <&pinctrl_uart3>;
 111                         clocks = <&peri_clk 3>;
 112                         clock-frequency = <36864000>;
 113                         resets = <&peri_rst 3>;
 114                 };
 115
 116                 gpio: gpio@55000000 {
 117                         compatible = "socionext,uniphier-gpio";
 118                         reg = <0x55000000 0x200>;
 119                         interrupt-parent = <&aidet>;
 120                         interrupt-controller;
 121                         #interrupt-cells = <2>;
 122                         gpio-controller;
 123                         #gpio-cells = <2>;
 124                         gpio-ranges = <&pinctrl 0 0 0>;
 125                         gpio-ranges-group-names = "gpio_range";
 126                         ngpios = <136>;
 127                         socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
 128                 };
 129
 130                 i2c0: i2c@58400000 {
 131                         compatible = "socionext,uniphier-i2c";
 132                         status = "disabled";
 133                         reg = <0x58400000 0x40>;
 134                         #address-cells = <1>;
 135                         #size-cells = <0>;
 136                         interrupts = <0 41 1>;
 137                         pinctrl-names = "default";
 138                         pinctrl-0 = <&pinctrl_i2c0>;
 139                         clocks = <&peri_clk 4>;
 140                         resets = <&peri_rst 4>;
 141                         clock-frequency = <100000>;
 142                 };
 143
 144                 i2c1: i2c@58480000 {
 145                         compatible = "socionext,uniphier-i2c";
 146                         status = "disabled";
 147                         reg = <0x58480000 0x40>;
 148                         #address-cells = <1>;
 149                         #size-cells = <0>;
 150                         interrupts = <0 42 1>;
 151                         pinctrl-names = "default";
 152                         pinctrl-0 = <&pinctrl_i2c1>;
 153                         clocks = <&peri_clk 5>;
 154                         resets = <&peri_rst 5>;
 155                         clock-frequency = <100000>;
 156                 };
 157
 158                 /* chip-internal connection for DMD */
 159                 i2c2: i2c@58500000 {
 160                         compatible = "socionext,uniphier-i2c";
 161                         reg = <0x58500000 0x40>;
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164                         interrupts = <0 43 1>;
 165                         pinctrl-names = "default";
 166                         pinctrl-0 = <&pinctrl_i2c2>;
 167                         clocks = <&peri_clk 6>;
 168                         resets = <&peri_rst 6>;
 169                         clock-frequency = <400000>;
 170                 };
 171
 172                 i2c3: i2c@58580000 {
 173                         compatible = "socionext,uniphier-i2c";
 174                         status = "disabled";
 175                         reg = <0x58580000 0x40>;
 176                         #address-cells = <1>;
 177                         #size-cells = <0>;
 178                         interrupts = <0 44 1>;
 179                         pinctrl-names = "default";
 180                         pinctrl-0 = <&pinctrl_i2c3>;
 181                         clocks = <&peri_clk 7>;
 182                         resets = <&peri_rst 7>;
 183                         clock-frequency = <100000>;
 184                 };
 185
 186                 system_bus: system-bus@58c00000 {
 187                         compatible = "socionext,uniphier-system-bus";
 188                         status = "disabled";
 189                         reg = <0x58c00000 0x400>;
 190                         #address-cells = <2>;
 191                         #size-cells = <1>;
 192                         pinctrl-names = "default";
 193                         pinctrl-0 = <&pinctrl_system_bus>;
 194                 };
 195
 196                 smpctrl@59801000 {
 197                         compatible = "socionext,uniphier-smpctrl";
 198                         reg = <0x59801000 0x400>;
 199                 };
 200
 201                 mioctrl@59810000 {
 202                         compatible = "socionext,uniphier-ld4-mioctrl",
 203                                      "simple-mfd", "syscon";
 204                         reg = <0x59810000 0x800>;
 205
 206                         mio_clk: clock {
 207                                 compatible = "socionext,uniphier-ld4-mio-clock";
 208                                 #clock-cells = <1>;
 209                         };
 210
 211                         mio_rst: reset {
 212                                 compatible = "socionext,uniphier-ld4-mio-reset";
 213                                 #reset-cells = <1>;
 214                         };
 215                 };
 216
 217                 perictrl@59820000 {
 218                         compatible = "socionext,uniphier-ld4-perictrl",
 219                                      "simple-mfd", "syscon";
 220                         reg = <0x59820000 0x200>;
 221
 222                         peri_clk: clock {
 223                                 compatible = "socionext,uniphier-ld4-peri-clock";
 224                                 #clock-cells = <1>;
 225                         };
 226
 227                         peri_rst: reset {
 228                                 compatible = "socionext,uniphier-ld4-peri-reset";
 229                                 #reset-cells = <1>;
 230                         };
 231                 };
 232
 233                 sd: sdhc@5a400000 {
 234                         compatible = "socionext,uniphier-sdhc";
 235                         status = "disabled";
 236                         reg = <0x5a400000 0x200>;
 237                         interrupts = <0 76 4>;
 238                         pinctrl-names = "default", "1.8v";
 239                         pinctrl-0 = <&pinctrl_sd>;
 240                         pinctrl-1 = <&pinctrl_sd_1v8>;
 241                         clocks = <&mio_clk 0>;
 242                         reset-names = "host", "bridge";
 243                         resets = <&mio_rst 0>, <&mio_rst 3>;
 244                         bus-width = <4>;
 245                         cap-sd-highspeed;
 246                         sd-uhs-sdr12;
 247                         sd-uhs-sdr25;
 248                         sd-uhs-sdr50;
 249                 };
 250
 251                 emmc: sdhc@5a500000 {
 252                         compatible = "socionext,uniphier-sdhc";
 253                         status = "disabled";
 254                         reg = <0x5a500000 0x200>;
 255                         interrupts = <0 78 4>;
 256                         pinctrl-names = "default", "1.8v";
 257                         pinctrl-0 = <&pinctrl_emmc>;
 258                         pinctrl-1 = <&pinctrl_emmc_1v8>;
 259                         clocks = <&mio_clk 1>;
 260                         reset-names = "host", "bridge";
 261                         resets = <&mio_rst 1>, <&mio_rst 4>;
 262                         bus-width = <8>;
 263                         non-removable;
 264                         cap-mmc-highspeed;
 265                         cap-mmc-hw-reset;
 266                 };
 267
 268                 usb0: usb@5a800100 {
 269                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 270                         status = "disabled";
 271                         reg = <0x5a800100 0x100>;
 272                         interrupts = <0 80 4>;
 273                         pinctrl-names = "default";
 274                         pinctrl-0 = <&pinctrl_usb0>;
 275                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
 276                                  <&mio_clk 12>;
 277                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 278                                  <&mio_rst 12>;
 279                         has-transaction-translator;
 280                 };
 281
 282                 usb1: usb@5a810100 {
 283                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 284                         status = "disabled";
 285                         reg = <0x5a810100 0x100>;
 286                         interrupts = <0 81 4>;
 287                         pinctrl-names = "default";
 288                         pinctrl-0 = <&pinctrl_usb1>;
 289                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
 290                                  <&mio_clk 13>;
 291                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 292                                  <&mio_rst 13>;
 293                         has-transaction-translator;
 294                 };
 295
 296                 usb2: usb@5a820100 {
 297                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 298                         status = "disabled";
 299                         reg = <0x5a820100 0x100>;
 300                         interrupts = <0 82 4>;
 301                         pinctrl-names = "default";
 302                         pinctrl-0 = <&pinctrl_usb2>;
 303                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
 304                                  <&mio_clk 14>;
 305                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 306                                  <&mio_rst 14>;
 307                         has-transaction-translator;
 308                 };
 309
 310                 soc-glue@5f800000 {
 311                         compatible = "socionext,uniphier-ld4-soc-glue",
 312                                      "simple-mfd", "syscon";
 313                         reg = <0x5f800000 0x2000>;
 314
 315                         pinctrl: pinctrl {
 316                                 compatible = "socionext,uniphier-ld4-pinctrl";
 317                         };
 318                 };
 319
 320                 soc-glue@5f900000 {
 321                         compatible = "socionext,uniphier-ld4-soc-glue-debug",
 322                                      "simple-mfd";
 323                         #address-cells = <1>;
 324                         #size-cells = <1>;
 325                         ranges = <0 0x5f900000 0x2000>;
 326
 327                         efuse@100 {
 328                                 compatible = "socionext,uniphier-efuse";
 329                                 reg = <0x100 0x28>;
 330                         };
 331
 332                         efuse@130 {
 333                                 compatible = "socionext,uniphier-efuse";
 334                                 reg = <0x130 0x8>;
 335                         };
 336                 };
 337
 338                 timer@60000200 {
 339                         compatible = "arm,cortex-a9-global-timer";
 340                         reg = <0x60000200 0x20>;
 341                         interrupts = <1 11 0x104>;
 342                         clocks = <&arm_timer_clk>;
 343                 };
 344
 345                 timer@60000600 {
 346                         compatible = "arm,cortex-a9-twd-timer";
 347                         reg = <0x60000600 0x20>;
 348                         interrupts = <1 13 0x104>;
 349                         clocks = <&arm_timer_clk>;
 350                 };
 351
 352                 intc: interrupt-controller@60001000 {
 353                         compatible = "arm,cortex-a9-gic";
 354                         reg = <0x60001000 0x1000>,
 355                               <0x60000100 0x100>;
 356                         #interrupt-cells = <3>;
 357                         interrupt-controller;
 358                 };
 359
 360                 aidet: aidet@61830000 {
 361                         compatible = "socionext,uniphier-ld4-aidet";
 362                         reg = <0x61830000 0x200>;
 363                         interrupt-controller;
 364                         #interrupt-cells = <2>;
 365                 };
 366
 367                 sysctrl@61840000 {
 368                         compatible = "socionext,uniphier-ld4-sysctrl",
 369                                      "simple-mfd", "syscon";
 370                         reg = <0x61840000 0x10000>;
 371
 372                         sys_clk: clock {
 373                                 compatible = "socionext,uniphier-ld4-clock";
 374                                 #clock-cells = <1>;
 375                         };
 376
 377                         sys_rst: reset {
 378                                 compatible = "socionext,uniphier-ld4-reset";
 379                                 #reset-cells = <1>;
 380                         };
 381                 };
 382
 383                 nand: nand@68000000 {
 384                         compatible = "socionext,uniphier-denali-nand-v5a";
 385                         status = "disabled";
 386                         reg-names = "nand_data", "denali_reg";
 387                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 388                         interrupts = <0 65 4>;
 389                         pinctrl-names = "default";
 390                         pinctrl-0 = <&pinctrl_nand2cs>;
 391                         clocks = <&sys_clk 2>;
 392                         resets = <&sys_rst 2>;
 393                 };
 394         };
 395 };
 396
 397 #include "uniphier-pinctrl.dtsi"