git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-ph1-ld11.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-LD11 SoC
   3  *
   4  * Copyright (C) 2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+        X11
   8  */
   9
  10 /memreserve/ 0x80000000 0x00000008;     /* cpu-release-addr */
  11
  12 / {
  13         compatible = "socionext,ph1-ld11";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&gic>;
  17
  18         cpus {
  19                 #address-cells = <2>;
  20                 #size-cells = <0>;
  21
  22                 cpu-map {
  23                         cluster0 {
  24                                 core0 {
  25                                         cpu = <&cpu0>;
  26                                 };
  27                                 core1 {
  28                                         cpu = <&cpu1>;
  29                                 };
  30                         };
  31                 };
  32
  33                 cpu0: cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a53", "arm,armv8";
  36                         reg = <0 0x000>;
  37                         enable-method = "spin-table";
  38                         cpu-release-addr = <0 0x80000000>;
  39                 };
  40
  41                 cpu1: cpu@1 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a53", "arm,armv8";
  44                         reg = <0 0x001>;
  45                         enable-method = "spin-table";
  46                         cpu-release-addr = <0 0x80000000>;
  47                 };
  48         };
  49
  50         clocks {
  51                 refclk: ref {
  52                         compatible = "fixed-clock";
  53                         #clock-cells = <0>;
  54                         clock-frequency = <25000000>;
  55                 };
  56
  57                 uart_clk: uart_clk {
  58                         #clock-cells = <0>;
  59                         compatible = "fixed-clock";
  60                         clock-frequency = <58820000>;
  61                 };
  62
  63                 i2c_clk: i2c_clk {
  64                         #clock-cells = <0>;
  65                         compatible = "fixed-clock";
  66                         clock-frequency = <50000000>;
  67                 };
  68         };
  69
  70         timer {
  71                 compatible = "arm,armv8-timer";
  72                 interrupts = <1 13 0xf01>,
  73                              <1 14 0xf01>,
  74                              <1 11 0xf01>,
  75                              <1 10 0xf01>;
  76         };
  77
  78         soc {
  79                 compatible = "simple-bus";
  80                 #address-cells = <1>;
  81                 #size-cells = <1>;
  82                 ranges = <0 0 0 0xffffffff>;
  83                 u-boot,dm-pre-reloc;
  84
  85                 serial0: serial@54006800 {
  86                         compatible = "socionext,uniphier-uart";
  87                         status = "disabled";
  88                         reg = <0x54006800 0x40>;
  89                         interrupts = <0 33 4>;
  90                         pinctrl-names = "default";
  91                         pinctrl-0 = <&pinctrl_uart0>;
  92                         clocks = <&uart_clk>;
  93                         clock-frequency = <58820000>;
  94                 };
  95
  96                 serial1: serial@54006900 {
  97                         compatible = "socionext,uniphier-uart";
  98                         status = "disabled";
  99                         reg = <0x54006900 0x40>;
 100                         interrupts = <0 35 4>;
 101                         pinctrl-names = "default";
 102                         pinctrl-0 = <&pinctrl_uart1>;
 103                         clocks = <&uart_clk>;
 104                         clock-frequency = <58820000>;
 105                 };
 106
 107                 serial2: serial@54006a00 {
 108                         compatible = "socionext,uniphier-uart";
 109                         status = "disabled";
 110                         reg = <0x54006a00 0x40>;
 111                         interrupts = <0 37 4>;
 112                         pinctrl-names = "default";
 113                         pinctrl-0 = <&pinctrl_uart2>;
 114                         clocks = <&uart_clk>;
 115                         clock-frequency = <58820000>;
 116                 };
 117
 118                 serial3: serial@54006b00 {
 119                         compatible = "socionext,uniphier-uart";
 120                         status = "disabled";
 121                         reg = <0x54006b00 0x40>;
 122                         interrupts = <0 177 4>;
 123                         pinctrl-names = "default";
 124                         pinctrl-0 = <&pinctrl_uart3>;
 125                         clocks = <&uart_clk>;
 126                         clock-frequency = <58820000>;
 127                 };
 128
 129                 i2c0: i2c@58780000 {
 130                         compatible = "socionext,uniphier-fi2c";
 131                         status = "disabled";
 132                         reg = <0x58780000 0x80>;
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135                         interrupts = <0 41 4>;
 136                         pinctrl-names = "default";
 137                         pinctrl-0 = <&pinctrl_i2c0>;
 138                         clocks = <&i2c_clk>;
 139                         clock-frequency = <100000>;
 140                 };
 141
 142                 i2c1: i2c@58781000 {
 143                         compatible = "socionext,uniphier-fi2c";
 144                         status = "disabled";
 145                         reg = <0x58781000 0x80>;
 146                         #address-cells = <1>;
 147                         #size-cells = <0>;
 148                         interrupts = <0 42 4>;
 149                         pinctrl-names = "default";
 150                         pinctrl-0 = <&pinctrl_i2c1>;
 151                         clocks = <&i2c_clk>;
 152                         clock-frequency = <100000>;
 153                 };
 154
 155                 i2c2: i2c@58782000 {
 156                         compatible = "socionext,uniphier-fi2c";
 157                         reg = <0x58782000 0x80>;
 158                         #address-cells = <1>;
 159                         #size-cells = <0>;
 160                         interrupts = <0 43 4>;
 161                         clocks = <&i2c_clk>;
 162                         clock-frequency = <400000>;
 163                 };
 164
 165                 i2c3: i2c@58783000 {
 166                         compatible = "socionext,uniphier-fi2c";
 167                         status = "disabled";
 168                         reg = <0x58783000 0x80>;
 169                         #address-cells = <1>;
 170                         #size-cells = <0>;
 171                         interrupts = <0 44 4>;
 172                         pinctrl-names = "default";
 173                         pinctrl-0 = <&pinctrl_i2c3>;
 174                         clocks = <&i2c_clk>;
 175                         clock-frequency = <100000>;
 176                 };
 177
 178                 i2c4: i2c@58784000 {
 179                         compatible = "socionext,uniphier-fi2c";
 180                         status = "disabled";
 181                         reg = <0x58784000 0x80>;
 182                         #address-cells = <1>;
 183                         #size-cells = <0>;
 184                         interrupts = <0 45 4>;
 185                         pinctrl-names = "default";
 186                         pinctrl-0 = <&pinctrl_i2c4>;
 187                         clocks = <&i2c_clk>;
 188                         clock-frequency = <100000>;
 189                 };
 190
 191                 i2c5: i2c@58785000 {
 192                         compatible = "socionext,uniphier-fi2c";
 193                         reg = <0x58785000 0x80>;
 194                         #address-cells = <1>;
 195                         #size-cells = <0>;
 196                         interrupts = <0 25 4>;
 197                         clocks = <&i2c_clk>;
 198                         clock-frequency = <400000>;
 199                 };
 200
 201                 system_bus: system-bus@58c00000 {
 202                         compatible = "socionext,uniphier-system-bus";
 203                         status = "disabled";
 204                         reg = <0x58c00000 0x400>;
 205                         #address-cells = <2>;
 206                         #size-cells = <1>;
 207                         pinctrl-names = "default";
 208                         pinctrl-0 = <&pinctrl_system_bus>;
 209                 };
 210
 211                 smpctrl@59800000 {
 212                         compatible = "socionext,uniphier-smpctrl";
 213                         reg = <0x59801000 0x400>;
 214                 };
 215
 216                 usb0: usb@5a800100 {
 217                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 218                         status = "disabled";
 219                         reg = <0x5a800100 0x100>;
 220                         interrupts = <0 243 4>;
 221                         pinctrl-names = "default";
 222                         pinctrl-0 = <&pinctrl_usb0>;
 223                         clocks = <&mio 3>, <&mio 6>;
 224                 };
 225
 226                 usb1: usb@5a810100 {
 227                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 228                         status = "disabled";
 229                         reg = <0x5a810100 0x100>;
 230                         interrupts = <0 244 4>;
 231                         pinctrl-names = "default";
 232                         pinctrl-0 = <&pinctrl_usb1>;
 233                         clocks = <&mio 4>, <&mio 6>;
 234                 };
 235
 236                 usb2: usb@5a820100 {
 237                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 238                         status = "disabled";
 239                         reg = <0x5a820100 0x100>;
 240                         interrupts = <0 245 4>;
 241                         pinctrl-names = "default";
 242                         pinctrl-0 = <&pinctrl_usb2>;
 243                         clocks = <&mio 5>, <&mio 6>;
 244                 };
 245
 246                 mio: mioctrl@5b3e0000 {
 247                         compatible = "socionext,ph1-ld11-mioctrl";
 248                         reg = <0x5b3e0000 0x800>;
 249                         #clock-cells = <1>;
 250                 };
 251
 252                 soc-glue@5f800000 {
 253                         compatible = "simple-mfd", "syscon";
 254                         reg = <0x5f800000 0x2000>;
 255                         u-boot,dm-pre-reloc;
 256
 257                         pinctrl: pinctrl {
 258                                 compatible = "socionext,uniphier-ld11-pinctrl";
 259                                 u-boot,dm-pre-reloc;
 260                         };
 261                 };
 262
 263                 aidet@5fc20000 {
 264                         compatible = "simple-mfd", "syscon";
 265                         reg = <0x5fc20000 0x200>;
 266                 };
 267
 268                 gic: interrupt-controller@5fe00000 {
 269                         compatible = "arm,gic-v3";
 270                         reg = <0x5fe00000 0x10000>,     /* GICD */
 271                               <0x5fe40000 0x80000>;     /* GICR */
 272                         interrupt-controller;
 273                         #interrupt-cells = <3>;
 274                         interrupts = <1 9 4>;
 275                 };
 276         };
 277 };
 278
 279 /include/ "uniphier-pinctrl.dtsi"