2 * Device Tree Source for UniPhier PH1-LD11 SoC
4 * Copyright (C) 2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: GPL-2.0+ X11
10 /memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
13 compatible = "socionext,ph1-ld11";
16 interrupt-parent = <&gic>;
35 compatible = "arm,cortex-a53", "arm,armv8";
37 enable-method = "spin-table";
38 cpu-release-addr = <0 0x80000000>;
43 compatible = "arm,cortex-a53", "arm,armv8";
45 enable-method = "spin-table";
46 cpu-release-addr = <0 0x80000000>;
52 compatible = "fixed-clock";
54 clock-frequency = <25000000>;
59 compatible = "fixed-clock";
60 clock-frequency = <58820000>;
65 compatible = "fixed-clock";
66 clock-frequency = <50000000>;
71 compatible = "arm,armv8-timer";
72 interrupts = <1 13 0xf01>,
79 compatible = "simple-bus";
82 ranges = <0 0 0 0xffffffff>;
85 serial0: serial@54006800 {
86 compatible = "socionext,uniphier-uart";
88 reg = <0x54006800 0x40>;
89 interrupts = <0 33 4>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_uart0>;
93 clock-frequency = <58820000>;
96 serial1: serial@54006900 {
97 compatible = "socionext,uniphier-uart";
99 reg = <0x54006900 0x40>;
100 interrupts = <0 35 4>;
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_uart1>;
103 clocks = <&uart_clk>;
104 clock-frequency = <58820000>;
107 serial2: serial@54006a00 {
108 compatible = "socionext,uniphier-uart";
110 reg = <0x54006a00 0x40>;
111 interrupts = <0 37 4>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_uart2>;
114 clocks = <&uart_clk>;
115 clock-frequency = <58820000>;
118 serial3: serial@54006b00 {
119 compatible = "socionext,uniphier-uart";
121 reg = <0x54006b00 0x40>;
122 interrupts = <0 177 4>;
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_uart3>;
125 clocks = <&uart_clk>;
126 clock-frequency = <58820000>;
130 compatible = "socionext,uniphier-fi2c";
132 reg = <0x58780000 0x80>;
133 #address-cells = <1>;
135 interrupts = <0 41 4>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_i2c0>;
139 clock-frequency = <100000>;
143 compatible = "socionext,uniphier-fi2c";
145 reg = <0x58781000 0x80>;
146 #address-cells = <1>;
148 interrupts = <0 42 4>;
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_i2c1>;
152 clock-frequency = <100000>;
156 compatible = "socionext,uniphier-fi2c";
157 reg = <0x58782000 0x80>;
158 #address-cells = <1>;
160 interrupts = <0 43 4>;
162 clock-frequency = <400000>;
166 compatible = "socionext,uniphier-fi2c";
168 reg = <0x58783000 0x80>;
169 #address-cells = <1>;
171 interrupts = <0 44 4>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_i2c3>;
175 clock-frequency = <100000>;
179 compatible = "socionext,uniphier-fi2c";
181 reg = <0x58784000 0x80>;
182 #address-cells = <1>;
184 interrupts = <0 45 4>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_i2c4>;
188 clock-frequency = <100000>;
192 compatible = "socionext,uniphier-fi2c";
193 reg = <0x58785000 0x80>;
194 #address-cells = <1>;
196 interrupts = <0 25 4>;
198 clock-frequency = <400000>;
201 system_bus: system-bus@58c00000 {
202 compatible = "socionext,uniphier-system-bus";
204 reg = <0x58c00000 0x400>;
205 #address-cells = <2>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_system_bus>;
212 compatible = "socionext,uniphier-smpctrl";
213 reg = <0x59801000 0x400>;
217 compatible = "socionext,uniphier-ehci", "generic-ehci";
219 reg = <0x5a800100 0x100>;
220 interrupts = <0 243 4>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_usb0>;
223 clocks = <&mio 3>, <&mio 6>;
227 compatible = "socionext,uniphier-ehci", "generic-ehci";
229 reg = <0x5a810100 0x100>;
230 interrupts = <0 244 4>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_usb1>;
233 clocks = <&mio 4>, <&mio 6>;
237 compatible = "socionext,uniphier-ehci", "generic-ehci";
239 reg = <0x5a820100 0x100>;
240 interrupts = <0 245 4>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_usb2>;
243 clocks = <&mio 5>, <&mio 6>;
246 mio: mioctrl@5b3e0000 {
247 compatible = "socionext,ph1-ld11-mioctrl";
248 reg = <0x5b3e0000 0x800>;
253 compatible = "simple-mfd", "syscon";
254 reg = <0x5f800000 0x2000>;
258 compatible = "socionext,uniphier-ld11-pinctrl";
264 compatible = "simple-mfd", "syscon";
265 reg = <0x5fc20000 0x200>;
268 gic: interrupt-controller@5fe00000 {
269 compatible = "arm,gic-v3";
270 reg = <0x5fe00000 0x10000>, /* GICD */
271 <0x5fe40000 0x80000>; /* GICR */
272 interrupt-controller;
273 #interrupt-cells = <3>;
274 interrupts = <1 9 4>;
279 /include/ "uniphier-pinctrl.dtsi"