git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-ph1-ld11.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-LD11 SoC
   3  *
   4  * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 / {
  10         compatible = "socionext,ph1-ld11";
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13         interrupt-parent = <&gic>;
  14
  15         cpus {
  16                 #address-cells = <2>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a53", "arm,armv8";
  22                         reg = <0 0x000>;
  23                         enable-method = "spin-table";
  24                         cpu-release-addr = <0 0x80000100>;
  25                 };
  26
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a53", "arm,armv8";
  30                         reg = <0 0x001>;
  31                         enable-method = "spin-table";
  32                         cpu-release-addr = <0 0x80000100>;
  33                 };
  34         };
  35
  36         clocks {
  37                 uart_clk: uart_clk {
  38                         #clock-cells = <0>;
  39                         compatible = "fixed-clock";
  40                         clock-frequency = <58820000>;
  41                 };
  42
  43                 i2c_clk: i2c_clk {
  44                         #clock-cells = <0>;
  45                         compatible = "fixed-clock";
  46                         clock-frequency = <50000000>;
  47                 };
  48         };
  49
  50         timer {
  51                 compatible = "arm,armv8-timer";
  52                 interrupts = <1 13 0xf01>,
  53                              <1 14 0xf01>,
  54                              <1 11 0xf01>,
  55                              <1 10 0xf01>;
  56         };
  57
  58         soc {
  59                 compatible = "simple-bus";
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 ranges = <0 0 0 0xffffffff>;
  63
  64                 serial0: serial@54006800 {
  65                         compatible = "socionext,uniphier-uart";
  66                         status = "disabled";
  67                         reg = <0x54006800 0x40>;
  68                         interrupts = <0 33 4>;
  69                         pinctrl-names = "default";
  70                         pinctrl-0 = <&pinctrl_uart0>;
  71                         clocks = <&uart_clk>;
  72                 };
  73
  74                 serial1: serial@54006900 {
  75                         compatible = "socionext,uniphier-uart";
  76                         status = "disabled";
  77                         reg = <0x54006900 0x40>;
  78                         interrupts = <0 35 4>;
  79                         pinctrl-names = "default";
  80                         pinctrl-0 = <&pinctrl_uart1>;
  81                         clocks = <&uart_clk>;
  82                 };
  83
  84                 serial2: serial@54006a00 {
  85                         compatible = "socionext,uniphier-uart";
  86                         status = "disabled";
  87                         reg = <0x54006a00 0x40>;
  88                         interrupts = <0 37 4>;
  89                         pinctrl-names = "default";
  90                         pinctrl-0 = <&pinctrl_uart2>;
  91                         clocks = <&uart_clk>;
  92                 };
  93
  94                 serial3: serial@54006b00 {
  95                         compatible = "socionext,uniphier-uart";
  96                         status = "disabled";
  97                         reg = <0x54006b00 0x40>;
  98                         interrupts = <0 177 4>;
  99                         pinctrl-names = "default";
 100                         pinctrl-0 = <&pinctrl_uart3>;
 101                         clocks = <&uart_clk>;
 102                 };
 103
 104                 i2c0: i2c@58780000 {
 105                         compatible = "socionext,uniphier-fi2c";
 106                         status = "disabled";
 107                         reg = <0x58780000 0x80>;
 108                         #address-cells = <1>;
 109                         #size-cells = <0>;
 110                         interrupts = <0 41 4>;
 111                         pinctrl-names = "default";
 112                         pinctrl-0 = <&pinctrl_i2c0>;
 113                         clocks = <&i2c_clk>;
 114                         clock-frequency = <100000>;
 115                 };
 116
 117                 i2c1: i2c@58781000 {
 118                         compatible = "socionext,uniphier-fi2c";
 119                         status = "disabled";
 120                         reg = <0x58781000 0x80>;
 121                         #address-cells = <1>;
 122                         #size-cells = <0>;
 123                         interrupts = <0 42 4>;
 124                         pinctrl-names = "default";
 125                         pinctrl-0 = <&pinctrl_i2c1>;
 126                         clocks = <&i2c_clk>;
 127                         clock-frequency = <100000>;
 128                 };
 129
 130                 i2c2: i2c@58782000 {
 131                         compatible = "socionext,uniphier-fi2c";
 132                         reg = <0x58782000 0x80>;
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135                         interrupts = <0 43 4>;
 136                         clocks = <&i2c_clk>;
 137                         clock-frequency = <400000>;
 138                 };
 139
 140                 i2c3: i2c@58783000 {
 141                         compatible = "socionext,uniphier-fi2c";
 142                         status = "disabled";
 143                         reg = <0x58783000 0x80>;
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         interrupts = <0 44 4>;
 147                         pinctrl-names = "default";
 148                         pinctrl-0 = <&pinctrl_i2c3>;
 149                         clocks = <&i2c_clk>;
 150                         clock-frequency = <100000>;
 151                 };
 152
 153                 i2c4: i2c@58784000 {
 154                         compatible = "socionext,uniphier-fi2c";
 155                         status = "disabled";
 156                         reg = <0x58784000 0x80>;
 157                         #address-cells = <1>;
 158                         #size-cells = <0>;
 159                         interrupts = <0 45 4>;
 160                         pinctrl-names = "default";
 161                         pinctrl-0 = <&pinctrl_i2c4>;
 162                         clocks = <&i2c_clk>;
 163                         clock-frequency = <100000>;
 164                 };
 165
 166                 i2c5: i2c@58785000 {
 167                         compatible = "socionext,uniphier-fi2c";
 168                         reg = <0x58785000 0x80>;
 169                         #address-cells = <1>;
 170                         #size-cells = <0>;
 171                         interrupts = <0 25 4>;
 172                         clocks = <&i2c_clk>;
 173                         clock-frequency = <400000>;
 174                 };
 175
 176                 system_bus: system-bus@58c00000 {
 177                         compatible = "socionext,uniphier-system-bus";
 178                         status = "disabled";
 179                         reg = <0x58c00000 0x400>;
 180                         #address-cells = <2>;
 181                         #size-cells = <1>;
 182                 };
 183
 184                 smpctrl@59800000 {
 185                         compatible = "socionext,uniphier-smpctrl";
 186                         reg = <0x59801000 0x400>;
 187                 };
 188
 189                 pinctrl: pinctrl@5f801000 {
 190                         compatible = "socionext,ph1-ld11-pinctrl", "syscon";
 191                         reg = <0x5f801000 0xe00>;
 192                 };
 193
 194                 gic: interrupt-controller@5fe00000 {
 195                         compatible = "arm,gic-v3";
 196                         reg = <0x5fe00000 0x10000>,     /* GICD */
 197                               <0x5fe40000 0x80000>;     /* GICR */
 198                         interrupt-controller;
 199                         #interrupt-cells = <3>;
 200                         interrupts = <1 9 4>;
 201                 };
 202         };
 203 };
 204
 205 /include/ "uniphier-pinctrl.dtsi"