2 * Device Tree Source for UniPhier PH1-LD11 SoC
4 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
10 compatible = "socionext,ph1-ld11";
13 interrupt-parent = <&gic>;
21 compatible = "arm,cortex-a53", "arm,armv8";
23 enable-method = "spin-table";
24 cpu-release-addr = <0 0x80000100>;
29 compatible = "arm,cortex-a53", "arm,armv8";
31 enable-method = "spin-table";
32 cpu-release-addr = <0 0x80000100>;
39 compatible = "fixed-clock";
40 clock-frequency = <58820000>;
45 compatible = "fixed-clock";
46 clock-frequency = <50000000>;
51 compatible = "arm,armv8-timer";
52 interrupts = <1 13 0xf01>,
59 compatible = "simple-bus";
62 ranges = <0 0 0 0xffffffff>;
64 serial0: serial@54006800 {
65 compatible = "socionext,uniphier-uart";
67 reg = <0x54006800 0x40>;
68 interrupts = <0 33 4>;
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_uart0>;
74 serial1: serial@54006900 {
75 compatible = "socionext,uniphier-uart";
77 reg = <0x54006900 0x40>;
78 interrupts = <0 35 4>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_uart1>;
84 serial2: serial@54006a00 {
85 compatible = "socionext,uniphier-uart";
87 reg = <0x54006a00 0x40>;
88 interrupts = <0 37 4>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_uart2>;
94 serial3: serial@54006b00 {
95 compatible = "socionext,uniphier-uart";
97 reg = <0x54006b00 0x40>;
98 interrupts = <0 177 4>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_uart3>;
101 clocks = <&uart_clk>;
105 compatible = "socionext,uniphier-fi2c";
107 reg = <0x58780000 0x80>;
108 #address-cells = <1>;
110 interrupts = <0 41 4>;
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_i2c0>;
114 clock-frequency = <100000>;
118 compatible = "socionext,uniphier-fi2c";
120 reg = <0x58781000 0x80>;
121 #address-cells = <1>;
123 interrupts = <0 42 4>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_i2c1>;
127 clock-frequency = <100000>;
131 compatible = "socionext,uniphier-fi2c";
132 reg = <0x58782000 0x80>;
133 #address-cells = <1>;
135 interrupts = <0 43 4>;
137 clock-frequency = <400000>;
141 compatible = "socionext,uniphier-fi2c";
143 reg = <0x58783000 0x80>;
144 #address-cells = <1>;
146 interrupts = <0 44 4>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_i2c3>;
150 clock-frequency = <100000>;
154 compatible = "socionext,uniphier-fi2c";
156 reg = <0x58784000 0x80>;
157 #address-cells = <1>;
159 interrupts = <0 45 4>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_i2c4>;
163 clock-frequency = <100000>;
167 compatible = "socionext,uniphier-fi2c";
168 reg = <0x58785000 0x80>;
169 #address-cells = <1>;
171 interrupts = <0 25 4>;
173 clock-frequency = <400000>;
176 system_bus: system-bus@58c00000 {
177 compatible = "socionext,uniphier-system-bus";
179 reg = <0x58c00000 0x400>;
180 #address-cells = <2>;
185 compatible = "socionext,uniphier-smpctrl";
186 reg = <0x59801000 0x400>;
189 pinctrl: pinctrl@5f801000 {
190 compatible = "socionext,ph1-ld11-pinctrl", "syscon";
191 reg = <0x5f801000 0xe00>;
194 gic: interrupt-controller@5fe00000 {
195 compatible = "arm,gic-v3";
196 reg = <0x5fe00000 0x10000>, /* GICD */
197 <0x5fe40000 0x80000>; /* GICR */
198 interrupt-controller;
199 #interrupt-cells = <3>;
200 interrupts = <1 9 4>;
205 /include/ "uniphier-pinctrl.dtsi"