git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-ph1-ld20.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-LD20 SoC
   3  *
   4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /memreserve/ 0x80000000 0x00000008;     /* cpu-release-addr */
  10
  11 / {
  12         compatible = "socionext,ph1-ld20";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15         interrupt-parent = <&gic>;
  16
  17         cpus {
  18                 #address-cells = <2>;
  19                 #size-cells = <0>;
  20
  21                 cpu-map {
  22                         cluster0 {
  23                                 core0 {
  24                                         cpu = <&cpu0>;
  25                                 };
  26                                 core1 {
  27                                         cpu = <&cpu1>;
  28                                 };
  29                         };
  30
  31                         cluster1 {
  32                                 core0 {
  33                                         cpu = <&cpu2>;
  34                                 };
  35                                 core1 {
  36                                         cpu = <&cpu3>;
  37                                 };
  38                         };
  39                 };
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a72", "arm,armv8";
  44                         reg = <0 0x000>;
  45                         enable-method = "spin-table";
  46                         cpu-release-addr = <0 0x80000000>;
  47                 };
  48
  49                 cpu1: cpu@1 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a72", "arm,armv8";
  52                         reg = <0 0x001>;
  53                         enable-method = "spin-table";
  54                         cpu-release-addr = <0 0x80000000>;
  55                 };
  56
  57                 cpu2: cpu@100 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a53", "arm,armv8";
  60                         reg = <0 0x100>;
  61                         enable-method = "spin-table";
  62                         cpu-release-addr = <0 0x80000000>;
  63                 };
  64
  65                 cpu3: cpu@101 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         reg = <0 0x101>;
  69                         enable-method = "spin-table";
  70                         cpu-release-addr = <0 0x80000000>;
  71                 };
  72         };
  73
  74         clocks {
  75                 refclk: ref {
  76                         compatible = "fixed-clock";
  77                         #clock-cells = <0>;
  78                         clock-frequency = <25000000>;
  79                 };
  80
  81                 uart_clk: uart_clk {
  82                         #clock-cells = <0>;
  83                         compatible = "fixed-clock";
  84                         clock-frequency = <58820000>;
  85                 };
  86
  87                 i2c_clk: i2c_clk {
  88                         #clock-cells = <0>;
  89                         compatible = "fixed-clock";
  90                         clock-frequency = <50000000>;
  91                 };
  92         };
  93
  94         timer {
  95                 compatible = "arm,armv8-timer";
  96                 interrupts = <1 13 0xf01>,
  97                              <1 14 0xf01>,
  98                              <1 11 0xf01>,
  99                              <1 10 0xf01>;
 100         };
 101
 102         soc {
 103                 compatible = "simple-bus";
 104                 #address-cells = <1>;
 105                 #size-cells = <1>;
 106                 ranges = <0 0 0 0xffffffff>;
 107                 u-boot,dm-pre-reloc;
 108
 109                 serial0: serial@54006800 {
 110                         compatible = "socionext,uniphier-uart";
 111                         status = "disabled";
 112                         reg = <0x54006800 0x40>;
 113                         interrupts = <0 33 4>;
 114                         pinctrl-names = "default";
 115                         pinctrl-0 = <&pinctrl_uart0>;
 116                         clocks = <&uart_clk>;
 117                         clock-frequency = <58820000>;
 118                 };
 119
 120                 serial1: serial@54006900 {
 121                         compatible = "socionext,uniphier-uart";
 122                         status = "disabled";
 123                         reg = <0x54006900 0x40>;
 124                         interrupts = <0 35 4>;
 125                         pinctrl-names = "default";
 126                         pinctrl-0 = <&pinctrl_uart1>;
 127                         clocks = <&uart_clk>;
 128                         clock-frequency = <58820000>;
 129                 };
 130
 131                 serial2: serial@54006a00 {
 132                         compatible = "socionext,uniphier-uart";
 133                         status = "disabled";
 134                         reg = <0x54006a00 0x40>;
 135                         interrupts = <0 37 4>;
 136                         pinctrl-names = "default";
 137                         pinctrl-0 = <&pinctrl_uart2>;
 138                         clocks = <&uart_clk>;
 139                         clock-frequency = <58820000>;
 140                 };
 141
 142                 serial3: serial@54006b00 {
 143                         compatible = "socionext,uniphier-uart";
 144                         status = "disabled";
 145                         reg = <0x54006b00 0x40>;
 146                         interrupts = <0 177 4>;
 147                         pinctrl-names = "default";
 148                         pinctrl-0 = <&pinctrl_uart3>;
 149                         clocks = <&uart_clk>;
 150                         clock-frequency = <58820000>;
 151                 };
 152
 153                 i2c0: i2c@58780000 {
 154                         compatible = "socionext,uniphier-fi2c";
 155                         status = "disabled";
 156                         reg = <0x58780000 0x80>;
 157                         #address-cells = <1>;
 158                         #size-cells = <0>;
 159                         interrupts = <0 41 4>;
 160                         pinctrl-names = "default";
 161                         pinctrl-0 = <&pinctrl_i2c0>;
 162                         clocks = <&i2c_clk>;
 163                         clock-frequency = <100000>;
 164                 };
 165
 166                 i2c1: i2c@58781000 {
 167                         compatible = "socionext,uniphier-fi2c";
 168                         status = "disabled";
 169                         reg = <0x58781000 0x80>;
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172                         interrupts = <0 42 4>;
 173                         pinctrl-names = "default";
 174                         pinctrl-0 = <&pinctrl_i2c1>;
 175                         clocks = <&i2c_clk>;
 176                         clock-frequency = <100000>;
 177                 };
 178
 179                 i2c2: i2c@58782000 {
 180                         compatible = "socionext,uniphier-fi2c";
 181                         reg = <0x58782000 0x80>;
 182                         #address-cells = <1>;
 183                         #size-cells = <0>;
 184                         interrupts = <0 43 4>;
 185                         clocks = <&i2c_clk>;
 186                         clock-frequency = <400000>;
 187                 };
 188
 189                 i2c3: i2c@58783000 {
 190                         compatible = "socionext,uniphier-fi2c";
 191                         status = "disabled";
 192                         reg = <0x58783000 0x80>;
 193                         #address-cells = <1>;
 194                         #size-cells = <0>;
 195                         interrupts = <0 44 4>;
 196                         pinctrl-names = "default";
 197                         pinctrl-0 = <&pinctrl_i2c3>;
 198                         clocks = <&i2c_clk>;
 199                         clock-frequency = <100000>;
 200                 };
 201
 202                 i2c4: i2c@58784000 {
 203                         compatible = "socionext,uniphier-fi2c";
 204                         status = "disabled";
 205                         reg = <0x58784000 0x80>;
 206                         #address-cells = <1>;
 207                         #size-cells = <0>;
 208                         interrupts = <0 45 4>;
 209                         pinctrl-names = "default";
 210                         pinctrl-0 = <&pinctrl_i2c4>;
 211                         clocks = <&i2c_clk>;
 212                         clock-frequency = <100000>;
 213                 };
 214
 215                 i2c5: i2c@58785000 {
 216                         compatible = "socionext,uniphier-fi2c";
 217                         reg = <0x58785000 0x80>;
 218                         #address-cells = <1>;
 219                         #size-cells = <0>;
 220                         interrupts = <0 25 4>;
 221                         clocks = <&i2c_clk>;
 222                         clock-frequency = <400000>;
 223                 };
 224
 225                 system_bus: system-bus@58c00000 {
 226                         compatible = "socionext,uniphier-system-bus";
 227                         status = "disabled";
 228                         reg = <0x58c00000 0x400>;
 229                         #address-cells = <2>;
 230                         #size-cells = <1>;
 231                         pinctrl-names = "default";
 232                         pinctrl-0 = <&pinctrl_system_bus>;
 233                 };
 234
 235                 smpctrl@59800000 {
 236                         compatible = "socionext,uniphier-smpctrl";
 237                         reg = <0x59801000 0x400>;
 238                 };
 239
 240                 mio: mioctrl@59810000 {
 241                         compatible = "socionext,ph1-ld20-mioctrl";
 242                         reg = <0x59810000 0x800>;
 243                         #clock-cells = <1>;
 244                 };
 245
 246                 sd: sdhc@5a400000 {
 247                         compatible = "socionext,uniphier-sdhc";
 248                         status = "disabled";
 249                         reg = <0x5a400000 0x800>;
 250                         interrupts = <0 76 4>;
 251                         pinctrl-names = "default";
 252                         pinctrl-0 = <&pinctrl_sd>;
 253                         clocks = <&mio 0>;
 254                         bus-width = <4>;
 255                 };
 256
 257                 soc-glue@5f800000 {
 258                         compatible = "simple-mfd", "syscon";
 259                         reg = <0x5f800000 0x2000>;
 260                         u-boot,dm-pre-reloc;
 261
 262                         pinctrl: pinctrl {
 263                                 compatible = "socionext,uniphier-ld20-pinctrl";
 264                                 u-boot,dm-pre-reloc;
 265                         };
 266                 };
 267
 268                 aidet@5fc20000 {
 269                         compatible = "simple-mfd", "syscon";
 270                         reg = <0x5fc20000 0x200>;
 271                 };
 272
 273                 gic: interrupt-controller@5fe00000 {
 274                         compatible = "arm,gic-v3";
 275                         reg = <0x5fe00000 0x10000>,     /* GICD */
 276                               <0x5fe80000 0x80000>;     /* GICR */
 277                         interrupt-controller;
 278                         #interrupt-cells = <3>;
 279                         interrupts = <1 9 4>;
 280                 };
 281         };
 282 };
 283
 284 /include/ "uniphier-pinctrl.dtsi"