2 * Device Tree Source for UniPhier PH1-LD20 SoC
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
12 compatible = "socionext,ph1-ld20";
15 interrupt-parent = <&gic>;
43 compatible = "arm,cortex-a72", "arm,armv8";
45 enable-method = "spin-table";
46 cpu-release-addr = <0 0x80000000>;
51 compatible = "arm,cortex-a72", "arm,armv8";
53 enable-method = "spin-table";
54 cpu-release-addr = <0 0x80000000>;
59 compatible = "arm,cortex-a53", "arm,armv8";
61 enable-method = "spin-table";
62 cpu-release-addr = <0 0x80000000>;
67 compatible = "arm,cortex-a53", "arm,armv8";
69 enable-method = "spin-table";
70 cpu-release-addr = <0 0x80000000>;
76 compatible = "fixed-clock";
78 clock-frequency = <25000000>;
83 compatible = "fixed-clock";
84 clock-frequency = <58820000>;
89 compatible = "fixed-clock";
90 clock-frequency = <50000000>;
95 compatible = "arm,armv8-timer";
96 interrupts = <1 13 0xf01>,
103 compatible = "simple-bus";
104 #address-cells = <1>;
106 ranges = <0 0 0 0xffffffff>;
109 serial0: serial@54006800 {
110 compatible = "socionext,uniphier-uart";
112 reg = <0x54006800 0x40>;
113 interrupts = <0 33 4>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_uart0>;
116 clocks = <&uart_clk>;
117 clock-frequency = <58820000>;
120 serial1: serial@54006900 {
121 compatible = "socionext,uniphier-uart";
123 reg = <0x54006900 0x40>;
124 interrupts = <0 35 4>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_uart1>;
127 clocks = <&uart_clk>;
128 clock-frequency = <58820000>;
131 serial2: serial@54006a00 {
132 compatible = "socionext,uniphier-uart";
134 reg = <0x54006a00 0x40>;
135 interrupts = <0 37 4>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_uart2>;
138 clocks = <&uart_clk>;
139 clock-frequency = <58820000>;
142 serial3: serial@54006b00 {
143 compatible = "socionext,uniphier-uart";
145 reg = <0x54006b00 0x40>;
146 interrupts = <0 177 4>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_uart3>;
149 clocks = <&uart_clk>;
150 clock-frequency = <58820000>;
154 compatible = "socionext,uniphier-fi2c";
156 reg = <0x58780000 0x80>;
157 #address-cells = <1>;
159 interrupts = <0 41 4>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_i2c0>;
163 clock-frequency = <100000>;
167 compatible = "socionext,uniphier-fi2c";
169 reg = <0x58781000 0x80>;
170 #address-cells = <1>;
172 interrupts = <0 42 4>;
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_i2c1>;
176 clock-frequency = <100000>;
180 compatible = "socionext,uniphier-fi2c";
181 reg = <0x58782000 0x80>;
182 #address-cells = <1>;
184 interrupts = <0 43 4>;
186 clock-frequency = <400000>;
190 compatible = "socionext,uniphier-fi2c";
192 reg = <0x58783000 0x80>;
193 #address-cells = <1>;
195 interrupts = <0 44 4>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_i2c3>;
199 clock-frequency = <100000>;
203 compatible = "socionext,uniphier-fi2c";
205 reg = <0x58784000 0x80>;
206 #address-cells = <1>;
208 interrupts = <0 45 4>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_i2c4>;
212 clock-frequency = <100000>;
216 compatible = "socionext,uniphier-fi2c";
217 reg = <0x58785000 0x80>;
218 #address-cells = <1>;
220 interrupts = <0 25 4>;
222 clock-frequency = <400000>;
225 system_bus: system-bus@58c00000 {
226 compatible = "socionext,uniphier-system-bus";
228 reg = <0x58c00000 0x400>;
229 #address-cells = <2>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_system_bus>;
236 compatible = "socionext,uniphier-smpctrl";
237 reg = <0x59801000 0x400>;
240 mio: mioctrl@59810000 {
241 compatible = "socionext,ph1-ld20-mioctrl";
242 reg = <0x59810000 0x800>;
247 compatible = "socionext,uniphier-sdhc";
249 reg = <0x5a400000 0x800>;
250 interrupts = <0 76 4>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_sd>;
258 compatible = "simple-mfd", "syscon";
259 reg = <0x5f800000 0x2000>;
263 compatible = "socionext,uniphier-ld20-pinctrl";
269 compatible = "simple-mfd", "syscon";
270 reg = <0x5fc20000 0x200>;
273 gic: interrupt-controller@5fe00000 {
274 compatible = "arm,gic-v3";
275 reg = <0x5fe00000 0x10000>, /* GICD */
276 <0x5fe80000 0x80000>; /* GICR */
277 interrupt-controller;
278 #interrupt-cells = <3>;
279 interrupts = <1 9 4>;
284 /include/ "uniphier-pinctrl.dtsi"