git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-ph1-ld20.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-LD20 SoC
   3  *
   4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /memreserve/ 0x80000000 0x00000008;     /* cpu-release-addr */
  10
  11 / {
  12         compatible = "socionext,ph1-ld20";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15         interrupt-parent = <&gic>;
  16
  17         cpus {
  18                 #address-cells = <2>;
  19                 #size-cells = <0>;
  20
  21                 cpu-map {
  22                         cluster0 {
  23                                 core0 {
  24                                         cpu = <&cpu0>;
  25                                 };
  26                                 core1 {
  27                                         cpu = <&cpu1>;
  28                                 };
  29                         };
  30
  31                         cluster1 {
  32                                 core0 {
  33                                         cpu = <&cpu2>;
  34                                 };
  35                                 core1 {
  36                                         cpu = <&cpu3>;
  37                                 };
  38                         };
  39                 };
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a72", "arm,armv8";
  44                         reg = <0 0x000>;
  45                         enable-method = "spin-table";
  46                         cpu-release-addr = <0 0x80000000>;
  47                 };
  48
  49                 cpu1: cpu@1 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a72", "arm,armv8";
  52                         reg = <0 0x001>;
  53                         enable-method = "spin-table";
  54                         cpu-release-addr = <0 0x80000000>;
  55                 };
  56
  57                 cpu2: cpu@100 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a53", "arm,armv8";
  60                         reg = <0 0x100>;
  61                         enable-method = "spin-table";
  62                         cpu-release-addr = <0 0x80000000>;
  63                 };
  64
  65                 cpu3: cpu@101 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         reg = <0 0x101>;
  69                         enable-method = "spin-table";
  70                         cpu-release-addr = <0 0x80000000>;
  71                 };
  72         };
  73
  74         clocks {
  75                 refclk: ref {
  76                         compatible = "fixed-clock";
  77                         #clock-cells = <0>;
  78                         clock-frequency = <25000000>;
  79                 };
  80
  81                 i2c_clk: i2c_clk {
  82                         #clock-cells = <0>;
  83                         compatible = "fixed-clock";
  84                         clock-frequency = <50000000>;
  85                 };
  86         };
  87
  88         timer {
  89                 compatible = "arm,armv8-timer";
  90                 interrupts = <1 13 4>,
  91                              <1 14 4>,
  92                              <1 11 4>,
  93                              <1 10 4>;
  94         };
  95
  96         soc {
  97                 compatible = "simple-bus";
  98                 #address-cells = <1>;
  99                 #size-cells = <1>;
 100                 ranges = <0 0 0 0xffffffff>;
 101                 u-boot,dm-pre-reloc;
 102
 103                 serial0: serial@54006800 {
 104                         compatible = "socionext,uniphier-uart";
 105                         status = "disabled";
 106                         reg = <0x54006800 0x40>;
 107                         interrupts = <0 33 4>;
 108                         pinctrl-names = "default";
 109                         pinctrl-0 = <&pinctrl_uart0>;
 110                         clocks = <&peri_clk 0>;
 111                         clock-frequency = <58820000>;
 112                 };
 113
 114                 serial1: serial@54006900 {
 115                         compatible = "socionext,uniphier-uart";
 116                         status = "disabled";
 117                         reg = <0x54006900 0x40>;
 118                         interrupts = <0 35 4>;
 119                         pinctrl-names = "default";
 120                         pinctrl-0 = <&pinctrl_uart1>;
 121                         clocks = <&peri_clk 1>;
 122                         clock-frequency = <58820000>;
 123                 };
 124
 125                 serial2: serial@54006a00 {
 126                         compatible = "socionext,uniphier-uart";
 127                         status = "disabled";
 128                         reg = <0x54006a00 0x40>;
 129                         interrupts = <0 37 4>;
 130                         pinctrl-names = "default";
 131                         pinctrl-0 = <&pinctrl_uart2>;
 132                         clocks = <&peri_clk 2>;
 133                         clock-frequency = <58820000>;
 134                 };
 135
 136                 serial3: serial@54006b00 {
 137                         compatible = "socionext,uniphier-uart";
 138                         status = "disabled";
 139                         reg = <0x54006b00 0x40>;
 140                         interrupts = <0 177 4>;
 141                         pinctrl-names = "default";
 142                         pinctrl-0 = <&pinctrl_uart3>;
 143                         clocks = <&peri_clk 3>;
 144                         clock-frequency = <58820000>;
 145                 };
 146
 147                 i2c0: i2c@58780000 {
 148                         compatible = "socionext,uniphier-fi2c";
 149                         status = "disabled";
 150                         reg = <0x58780000 0x80>;
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153                         interrupts = <0 41 4>;
 154                         pinctrl-names = "default";
 155                         pinctrl-0 = <&pinctrl_i2c0>;
 156                         clocks = <&i2c_clk>;
 157                         clock-frequency = <100000>;
 158                 };
 159
 160                 i2c1: i2c@58781000 {
 161                         compatible = "socionext,uniphier-fi2c";
 162                         status = "disabled";
 163                         reg = <0x58781000 0x80>;
 164                         #address-cells = <1>;
 165                         #size-cells = <0>;
 166                         interrupts = <0 42 4>;
 167                         pinctrl-names = "default";
 168                         pinctrl-0 = <&pinctrl_i2c1>;
 169                         clocks = <&i2c_clk>;
 170                         clock-frequency = <100000>;
 171                 };
 172
 173                 i2c2: i2c@58782000 {
 174                         compatible = "socionext,uniphier-fi2c";
 175                         reg = <0x58782000 0x80>;
 176                         #address-cells = <1>;
 177                         #size-cells = <0>;
 178                         interrupts = <0 43 4>;
 179                         clocks = <&i2c_clk>;
 180                         clock-frequency = <400000>;
 181                 };
 182
 183                 i2c3: i2c@58783000 {
 184                         compatible = "socionext,uniphier-fi2c";
 185                         status = "disabled";
 186                         reg = <0x58783000 0x80>;
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189                         interrupts = <0 44 4>;
 190                         pinctrl-names = "default";
 191                         pinctrl-0 = <&pinctrl_i2c3>;
 192                         clocks = <&i2c_clk>;
 193                         clock-frequency = <100000>;
 194                 };
 195
 196                 i2c4: i2c@58784000 {
 197                         compatible = "socionext,uniphier-fi2c";
 198                         status = "disabled";
 199                         reg = <0x58784000 0x80>;
 200                         #address-cells = <1>;
 201                         #size-cells = <0>;
 202                         interrupts = <0 45 4>;
 203                         pinctrl-names = "default";
 204                         pinctrl-0 = <&pinctrl_i2c4>;
 205                         clocks = <&i2c_clk>;
 206                         clock-frequency = <100000>;
 207                 };
 208
 209                 i2c5: i2c@58785000 {
 210                         compatible = "socionext,uniphier-fi2c";
 211                         reg = <0x58785000 0x80>;
 212                         #address-cells = <1>;
 213                         #size-cells = <0>;
 214                         interrupts = <0 25 4>;
 215                         clocks = <&i2c_clk>;
 216                         clock-frequency = <400000>;
 217                 };
 218
 219                 system_bus: system-bus@58c00000 {
 220                         compatible = "socionext,uniphier-system-bus";
 221                         status = "disabled";
 222                         reg = <0x58c00000 0x400>;
 223                         #address-cells = <2>;
 224                         #size-cells = <1>;
 225                         pinctrl-names = "default";
 226                         pinctrl-0 = <&pinctrl_system_bus>;
 227                 };
 228
 229                 smpctrl@59800000 {
 230                         compatible = "socionext,uniphier-smpctrl";
 231                         reg = <0x59801000 0x400>;
 232                 };
 233
 234                 mioctrl@59810000 {
 235                         compatible = "socionext,uniphier-mioctrl",
 236                                      "simple-mfd", "syscon";
 237                         reg = <0x59810000 0x800>;
 238
 239                         mio_clk: clock {
 240                                 compatible = "socionext,uniphier-ld20-mio-clock";
 241                                 #clock-cells = <1>;
 242                         };
 243
 244                         mio_rst: reset {
 245                                 compatible = "socionext,uniphier-ld20-mio-reset";
 246                                 #reset-cells = <1>;
 247                         };
 248                 };
 249
 250                 perictrl@59820000 {
 251                         compatible = "socionext,uniphier-perictrl",
 252                                      "simple-mfd", "syscon";
 253                         reg = <0x59820000 0x200>;
 254
 255                         peri_clk: clock {
 256                                 compatible = "socionext,uniphier-ld20-peri-clock";
 257                                 #clock-cells = <1>;
 258                         };
 259
 260                         peri_rst: reset {
 261                                 compatible = "socionext,uniphier-ld20-peri-reset";
 262                                 #reset-cells = <1>;
 263                         };
 264                 };
 265
 266                 sd: sdhc@5a400000 {
 267                         compatible = "socionext,uniphier-sdhc";
 268                         status = "disabled";
 269                         reg = <0x5a400000 0x800>;
 270                         interrupts = <0 76 4>;
 271                         pinctrl-names = "default";
 272                         pinctrl-0 = <&pinctrl_sd>;
 273                         clocks = <&mio_clk 0>;
 274                         bus-width = <4>;
 275                 };
 276
 277                 soc-glue@5f800000 {
 278                         compatible = "socionext,uniphier-soc-glue",
 279                                      "simple-mfd", "syscon";
 280                         reg = <0x5f800000 0x2000>;
 281                         u-boot,dm-pre-reloc;
 282
 283                         pinctrl: pinctrl {
 284                                 compatible = "socionext,uniphier-ld20-pinctrl";
 285                                 u-boot,dm-pre-reloc;
 286                         };
 287                 };
 288
 289                 aidet@5fc20000 {
 290                         compatible = "simple-mfd", "syscon";
 291                         reg = <0x5fc20000 0x200>;
 292                 };
 293
 294                 gic: interrupt-controller@5fe00000 {
 295                         compatible = "arm,gic-v3";
 296                         reg = <0x5fe00000 0x10000>,     /* GICD */
 297                               <0x5fe80000 0x80000>;     /* GICR */
 298                         interrupt-controller;
 299                         #interrupt-cells = <3>;
 300                         interrupts = <1 9 4>;
 301                 };
 302
 303                 sysctrl@61840000 {
 304                         compatible = "socionext,uniphier-sysctrl",
 305                                      "simple-mfd", "syscon";
 306                         reg = <0x61840000 0x4000>;
 307
 308                         sys_clk: clock {
 309                                 compatible = "socionext,uniphier-ld20-clock";
 310                                 #clock-cells = <1>;
 311                         };
 312
 313                         sys_rst: reset {
 314                                 compatible = "socionext,uniphier-ld20-reset";
 315                                 #reset-cells = <1>;
 316                         };
 317                 };
 318         };
 319 };
 320
 321 /include/ "uniphier-pinctrl.dtsi"