git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-ph1-ld20.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-LD20 SoC
   3  *
   4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 / {
  10         compatible = "socionext,ph1-ld20";
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13         interrupt-parent = <&gic>;
  14
  15         cpus {
  16                 #address-cells = <2>;
  17                 #size-cells = <0>;
  18
  19                 cpu-map {
  20                         cluster0 {
  21                                 core0 {
  22                                         cpu = <&cpu0>;
  23                                 };
  24                                 core1 {
  25                                         cpu = <&cpu1>;
  26                                 };
  27                         };
  28
  29                         cluster1 {
  30                                 core0 {
  31                                         cpu = <&cpu2>;
  32                                 };
  33                                 core1 {
  34                                         cpu = <&cpu3>;
  35                                 };
  36                         };
  37                 };
  38
  39                 cpu0: cpu@0 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a72", "arm,armv8";
  42                         reg = <0 0x000>;
  43                         enable-method = "spin-table";
  44                         cpu-release-addr = <0 0x80000100>;
  45                 };
  46
  47                 cpu1: cpu@1 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a72", "arm,armv8";
  50                         reg = <0 0x001>;
  51                         enable-method = "spin-table";
  52                         cpu-release-addr = <0 0x80000100>;
  53                 };
  54
  55                 cpu2: cpu@100 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a53", "arm,armv8";
  58                         reg = <0 0x100>;
  59                         enable-method = "spin-table";
  60                         cpu-release-addr = <0 0x80000100>;
  61                 };
  62
  63                 cpu3: cpu@101 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a53", "arm,armv8";
  66                         reg = <0 0x101>;
  67                         enable-method = "spin-table";
  68                         cpu-release-addr = <0 0x80000100>;
  69                 };
  70         };
  71
  72         clocks {
  73                 uart_clk: uart_clk {
  74                         #clock-cells = <0>;
  75                         compatible = "fixed-clock";
  76                         clock-frequency = <58820000>;
  77                 };
  78
  79                 i2c_clk: i2c_clk {
  80                         #clock-cells = <0>;
  81                         compatible = "fixed-clock";
  82                         clock-frequency = <50000000>;
  83                 };
  84         };
  85
  86         timer {
  87                 compatible = "arm,armv8-timer";
  88                 interrupts = <1 13 0xf01>,
  89                              <1 14 0xf01>,
  90                              <1 11 0xf01>,
  91                              <1 10 0xf01>;
  92         };
  93
  94         soc {
  95                 compatible = "simple-bus";
  96                 #address-cells = <1>;
  97                 #size-cells = <1>;
  98                 ranges = <0 0 0 0xffffffff>;
  99
 100                 serial0: serial@54006800 {
 101                         compatible = "socionext,uniphier-uart";
 102                         status = "disabled";
 103                         reg = <0x54006800 0x40>;
 104                         interrupts = <0 33 4>;
 105                         pinctrl-names = "default";
 106                         pinctrl-0 = <&pinctrl_uart0>;
 107                         clocks = <&uart_clk>;
 108                 };
 109
 110                 serial1: serial@54006900 {
 111                         compatible = "socionext,uniphier-uart";
 112                         status = "disabled";
 113                         reg = <0x54006900 0x40>;
 114                         interrupts = <0 35 4>;
 115                         pinctrl-names = "default";
 116                         pinctrl-0 = <&pinctrl_uart1>;
 117                         clocks = <&uart_clk>;
 118                 };
 119
 120                 serial2: serial@54006a00 {
 121                         compatible = "socionext,uniphier-uart";
 122                         status = "disabled";
 123                         reg = <0x54006a00 0x40>;
 124                         interrupts = <0 37 4>;
 125                         pinctrl-names = "default";
 126                         pinctrl-0 = <&pinctrl_uart2>;
 127                         clocks = <&uart_clk>;
 128                 };
 129
 130                 serial3: serial@54006b00 {
 131                         compatible = "socionext,uniphier-uart";
 132                         status = "disabled";
 133                         reg = <0x54006b00 0x40>;
 134                         interrupts = <0 177 4>;
 135                         pinctrl-names = "default";
 136                         pinctrl-0 = <&pinctrl_uart3>;
 137                         clocks = <&uart_clk>;
 138                 };
 139
 140                 i2c0: i2c@58780000 {
 141                         compatible = "socionext,uniphier-fi2c";
 142                         status = "disabled";
 143                         reg = <0x58780000 0x80>;
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         interrupts = <0 41 4>;
 147                         pinctrl-names = "default";
 148                         pinctrl-0 = <&pinctrl_i2c0>;
 149                         clocks = <&i2c_clk>;
 150                         clock-frequency = <100000>;
 151                 };
 152
 153                 i2c1: i2c@58781000 {
 154                         compatible = "socionext,uniphier-fi2c";
 155                         status = "disabled";
 156                         reg = <0x58781000 0x80>;
 157                         #address-cells = <1>;
 158                         #size-cells = <0>;
 159                         interrupts = <0 42 4>;
 160                         pinctrl-names = "default";
 161                         pinctrl-0 = <&pinctrl_i2c1>;
 162                         clocks = <&i2c_clk>;
 163                         clock-frequency = <100000>;
 164                 };
 165
 166                 i2c2: i2c@58782000 {
 167                         compatible = "socionext,uniphier-fi2c";
 168                         reg = <0x58782000 0x80>;
 169                         #address-cells = <1>;
 170                         #size-cells = <0>;
 171                         interrupts = <0 43 4>;
 172                         clocks = <&i2c_clk>;
 173                         clock-frequency = <400000>;
 174                 };
 175
 176                 i2c3: i2c@58783000 {
 177                         compatible = "socionext,uniphier-fi2c";
 178                         status = "disabled";
 179                         reg = <0x58783000 0x80>;
 180                         #address-cells = <1>;
 181                         #size-cells = <0>;
 182                         interrupts = <0 44 4>;
 183                         pinctrl-names = "default";
 184                         pinctrl-0 = <&pinctrl_i2c3>;
 185                         clocks = <&i2c_clk>;
 186                         clock-frequency = <100000>;
 187                 };
 188
 189                 i2c4: i2c@58784000 {
 190                         compatible = "socionext,uniphier-fi2c";
 191                         status = "disabled";
 192                         reg = <0x58784000 0x80>;
 193                         #address-cells = <1>;
 194                         #size-cells = <0>;
 195                         interrupts = <0 45 4>;
 196                         pinctrl-names = "default";
 197                         pinctrl-0 = <&pinctrl_i2c4>;
 198                         clocks = <&i2c_clk>;
 199                         clock-frequency = <100000>;
 200                 };
 201
 202                 i2c5: i2c@58785000 {
 203                         compatible = "socionext,uniphier-fi2c";
 204                         reg = <0x58785000 0x80>;
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207                         interrupts = <0 25 4>;
 208                         clocks = <&i2c_clk>;
 209                         clock-frequency = <400000>;
 210                 };
 211
 212                 system_bus: system-bus@58c00000 {
 213                         compatible = "socionext,uniphier-system-bus";
 214                         status = "disabled";
 215                         reg = <0x58c00000 0x400>;
 216                         #address-cells = <2>;
 217                         #size-cells = <1>;
 218                 };
 219
 220                 smpctrl@59800000 {
 221                         compatible = "socionext,uniphier-smpctrl";
 222                         reg = <0x59801000 0x400>;
 223                 };
 224
 225                 pinctrl: pinctrl@5f801000 {
 226                         compatible = "socionext,ph1-ld20-pinctrl", "syscon";
 227                         reg = <0x5f801000 0xe00>;
 228                 };
 229
 230                 gic: interrupt-controller@5fe00000 {
 231                         compatible = "arm,gic-v3";
 232                         reg = <0x5fe00000 0x10000>,     /* GICD */
 233                               <0x5fe80000 0x80000>;     /* GICR */
 234                         interrupt-controller;
 235                         #interrupt-cells = <3>;
 236                         interrupts = <1 9 4>;
 237                 };
 238         };
 239 };
 240
 241 /include/ "uniphier-pinctrl.dtsi"