2 * Device Tree Source for UniPhier PH1-LD20 SoC
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
10 compatible = "socionext,ph1-ld20";
13 interrupt-parent = <&gic>;
41 compatible = "arm,cortex-a72", "arm,armv8";
43 enable-method = "spin-table";
44 cpu-release-addr = <0 0x80000100>;
49 compatible = "arm,cortex-a72", "arm,armv8";
51 enable-method = "spin-table";
52 cpu-release-addr = <0 0x80000100>;
57 compatible = "arm,cortex-a53", "arm,armv8";
59 enable-method = "spin-table";
60 cpu-release-addr = <0 0x80000100>;
65 compatible = "arm,cortex-a53", "arm,armv8";
67 enable-method = "spin-table";
68 cpu-release-addr = <0 0x80000100>;
75 compatible = "fixed-clock";
76 clock-frequency = <58820000>;
81 compatible = "fixed-clock";
82 clock-frequency = <50000000>;
87 compatible = "arm,armv8-timer";
88 interrupts = <1 13 0xf01>,
95 compatible = "simple-bus";
98 ranges = <0 0 0 0xffffffff>;
100 serial0: serial@54006800 {
101 compatible = "socionext,uniphier-uart";
103 reg = <0x54006800 0x40>;
104 interrupts = <0 33 4>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_uart0>;
107 clocks = <&uart_clk>;
110 serial1: serial@54006900 {
111 compatible = "socionext,uniphier-uart";
113 reg = <0x54006900 0x40>;
114 interrupts = <0 35 4>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_uart1>;
117 clocks = <&uart_clk>;
120 serial2: serial@54006a00 {
121 compatible = "socionext,uniphier-uart";
123 reg = <0x54006a00 0x40>;
124 interrupts = <0 37 4>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_uart2>;
127 clocks = <&uart_clk>;
130 serial3: serial@54006b00 {
131 compatible = "socionext,uniphier-uart";
133 reg = <0x54006b00 0x40>;
134 interrupts = <0 177 4>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_uart3>;
137 clocks = <&uart_clk>;
141 compatible = "socionext,uniphier-fi2c";
143 reg = <0x58780000 0x80>;
144 #address-cells = <1>;
146 interrupts = <0 41 4>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_i2c0>;
150 clock-frequency = <100000>;
154 compatible = "socionext,uniphier-fi2c";
156 reg = <0x58781000 0x80>;
157 #address-cells = <1>;
159 interrupts = <0 42 4>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_i2c1>;
163 clock-frequency = <100000>;
167 compatible = "socionext,uniphier-fi2c";
168 reg = <0x58782000 0x80>;
169 #address-cells = <1>;
171 interrupts = <0 43 4>;
173 clock-frequency = <400000>;
177 compatible = "socionext,uniphier-fi2c";
179 reg = <0x58783000 0x80>;
180 #address-cells = <1>;
182 interrupts = <0 44 4>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_i2c3>;
186 clock-frequency = <100000>;
190 compatible = "socionext,uniphier-fi2c";
192 reg = <0x58784000 0x80>;
193 #address-cells = <1>;
195 interrupts = <0 45 4>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_i2c4>;
199 clock-frequency = <100000>;
203 compatible = "socionext,uniphier-fi2c";
204 reg = <0x58785000 0x80>;
205 #address-cells = <1>;
207 interrupts = <0 25 4>;
209 clock-frequency = <400000>;
212 system_bus: system-bus@58c00000 {
213 compatible = "socionext,uniphier-system-bus";
215 reg = <0x58c00000 0x400>;
216 #address-cells = <2>;
221 compatible = "socionext,uniphier-smpctrl";
222 reg = <0x59801000 0x400>;
225 pinctrl: pinctrl@5f801000 {
226 compatible = "socionext,ph1-ld20-pinctrl", "syscon";
227 reg = <0x5f801000 0xe00>;
230 gic: interrupt-controller@5fe00000 {
231 compatible = "arm,gic-v3";
232 reg = <0x5fe00000 0x10000>, /* GICD */
233 <0x5fe80000 0x80000>; /* GICR */
234 interrupt-controller;
235 #interrupt-cells = <3>;
236 interrupts = <1 9 4>;
241 /include/ "uniphier-pinctrl.dtsi"