2 * Device Tree Source for UniPhier PH1-LD4 SoC
4 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /include/ "skeleton.dtsi"
12 compatible = "socionext,ph1-ld4";
20 compatible = "arm,cortex-a9";
26 arm_timer_clk: arm_timer_clk {
28 compatible = "fixed-clock";
29 clock-frequency = <50000000>;
34 compatible = "simple-bus";
38 interrupt-parent = <&intc>;
41 compatible = "simple-bus";
46 uart0: serial@54006800 {
47 compatible = "socionext,uniphier-uart";
49 reg = <0x54006800 0x20>;
50 clock-frequency = <36864000>;
53 uart1: serial@54006900 {
54 compatible = "socionext,uniphier-uart";
56 reg = <0x54006900 0x20>;
57 clock-frequency = <36864000>;
60 uart2: serial@54006a00 {
61 compatible = "socionext,uniphier-uart";
63 reg = <0x54006a00 0x20>;
64 clock-frequency = <36864000>;
67 uart3: serial@54006b00 {
68 compatible = "socionext,uniphier-uart";
70 reg = <0x54006b00 0x20>;
71 clock-frequency = <36864000>;
75 compatible = "socionext,uniphier-i2c";
78 reg = <0x58400000 0x40>;
79 clock-frequency = <100000>;
84 compatible = "socionext,uniphier-i2c";
87 reg = <0x58480000 0x40>;
88 clock-frequency = <100000>;
93 compatible = "socionext,uniphier-i2c";
96 reg = <0x58500000 0x40>;
97 clock-frequency = <100000>;
102 compatible = "socionext,uniphier-i2c";
103 #address-cells = <1>;
105 reg = <0x58580000 0x40>;
106 clock-frequency = <100000>;
110 system-bus-controller-misc@59800000 {
111 compatible = "socionext,uniphier-system-bus-controller-misc",
113 reg = <0x59800000 0x2000>;
117 compatible = "socionext,uniphier-ehci", "generic-ehci";
119 reg = <0x5a800100 0x100>;
123 compatible = "socionext,uniphier-ehci", "generic-ehci";
125 reg = <0x5a810100 0x100>;
129 compatible = "socionext,uniphier-ehci", "generic-ehci";
131 reg = <0x5a820100 0x100>;
135 compatible = "arm,cortex-a9-global-timer";
136 reg = <0x60000200 0x20>;
137 interrupts = <1 11 0x104>;
138 clocks = <&arm_timer_clk>;
142 compatible = "arm,cortex-a9-twd-timer";
143 reg = <0x60000600 0x20>;
144 interrupts = <1 13 0x104>;
145 clocks = <&arm_timer_clk>;
148 intc: interrupt-controller@60001000 {
149 compatible = "arm,cortex-a9-gic";
150 #interrupt-cells = <3>;
151 interrupt-controller;
152 reg = <0x60001000 0x1000>,
156 nand: nand@68000000 {
157 compatible = "denali,denali-nand-dt";
158 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
159 reg-names = "nand_data", "denali_reg";