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[u-boot] / arch / arm / dts / uniphier-ph1-ld4.dtsi
1 /*
2  * Device Tree Source for UniPhier PH1-LD4 SoC
3  *
4  * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+        X11
7  */
8
9 /include/ "uniphier-common32.dtsi"
10
11 / {
12         compatible = "socionext,ph1-ld4";
13
14         cpus {
15                 #address-cells = <1>;
16                 #size-cells = <0>;
17
18                 cpu@0 {
19                         device_type = "cpu";
20                         compatible = "arm,cortex-a9";
21                         reg = <0>;
22                         next-level-cache = <&l2>;
23                 };
24         };
25
26         clocks {
27                 arm_timer_clk: arm_timer_clk {
28                         #clock-cells = <0>;
29                         compatible = "fixed-clock";
30                         clock-frequency = <50000000>;
31                 };
32
33                 uart_clk: uart_clk {
34                         #clock-cells = <0>;
35                         compatible = "fixed-clock";
36                         clock-frequency = <36864000>;
37                 };
38
39                 iobus_clk: iobus_clk {
40                         #clock-cells = <0>;
41                         compatible = "fixed-clock";
42                         clock-frequency = <100000000>;
43                 };
44         };
45 };
46
47 &soc {
48         l2: l2-cache@500c0000 {
49                 compatible = "socionext,uniphier-system-cache";
50                 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
51                 interrupts = <0 174 4>, <0 175 4>;
52                 cache-unified;
53                 cache-size = <(512 * 1024)>;
54                 cache-sets = <256>;
55                 cache-line-size = <128>;
56                 cache-level = <2>;
57         };
58
59         port0x: gpio@55000008 {
60                 compatible = "socionext,uniphier-gpio";
61                 reg = <0x55000008 0x8>;
62                 gpio-controller;
63                 #gpio-cells = <2>;
64         };
65
66         port1x: gpio@55000010 {
67                 compatible = "socionext,uniphier-gpio";
68                 reg = <0x55000010 0x8>;
69                 gpio-controller;
70                 #gpio-cells = <2>;
71         };
72
73         port2x: gpio@55000018 {
74                 compatible = "socionext,uniphier-gpio";
75                 reg = <0x55000018 0x8>;
76                 gpio-controller;
77                 #gpio-cells = <2>;
78         };
79
80         port3x: gpio@55000020 {
81                 compatible = "socionext,uniphier-gpio";
82                 reg = <0x55000020 0x8>;
83                 gpio-controller;
84                 #gpio-cells = <2>;
85         };
86
87         port4: gpio@55000028 {
88                 compatible = "socionext,uniphier-gpio";
89                 reg = <0x55000028 0x8>;
90                 gpio-controller;
91                 #gpio-cells = <2>;
92         };
93
94         port5x: gpio@55000030 {
95                 compatible = "socionext,uniphier-gpio";
96                 reg = <0x55000030 0x8>;
97                 gpio-controller;
98                 #gpio-cells = <2>;
99         };
100
101         port6x: gpio@55000038 {
102                 compatible = "socionext,uniphier-gpio";
103                 reg = <0x55000038 0x8>;
104                 gpio-controller;
105                 #gpio-cells = <2>;
106         };
107
108         port7x: gpio@55000040 {
109                 compatible = "socionext,uniphier-gpio";
110                 reg = <0x55000040 0x8>;
111                 gpio-controller;
112                 #gpio-cells = <2>;
113         };
114
115         port8x: gpio@55000048 {
116                 compatible = "socionext,uniphier-gpio";
117                 reg = <0x55000048 0x8>;
118                 gpio-controller;
119                 #gpio-cells = <2>;
120         };
121
122         port9x: gpio@55000050 {
123                 compatible = "socionext,uniphier-gpio";
124                 reg = <0x55000050 0x8>;
125                 gpio-controller;
126                 #gpio-cells = <2>;
127         };
128
129         port10x: gpio@55000058 {
130                 compatible = "socionext,uniphier-gpio";
131                 reg = <0x55000058 0x8>;
132                 gpio-controller;
133                 #gpio-cells = <2>;
134         };
135
136         port11x: gpio@55000060 {
137                 compatible = "socionext,uniphier-gpio";
138                 reg = <0x55000060 0x8>;
139                 gpio-controller;
140                 #gpio-cells = <2>;
141         };
142
143         port12x: gpio@55000068 {
144                 compatible = "socionext,uniphier-gpio";
145                 reg = <0x55000068 0x8>;
146                 gpio-controller;
147                 #gpio-cells = <2>;
148         };
149
150         port13x: gpio@55000070 {
151                 compatible = "socionext,uniphier-gpio";
152                 reg = <0x55000070 0x8>;
153                 gpio-controller;
154                 #gpio-cells = <2>;
155         };
156
157         port14x: gpio@55000078 {
158                 compatible = "socionext,uniphier-gpio";
159                 reg = <0x55000078 0x8>;
160                 gpio-controller;
161                 #gpio-cells = <2>;
162         };
163
164         port16x: gpio@55000088 {
165                 compatible = "socionext,uniphier-gpio";
166                 reg = <0x55000088 0x8>;
167                 gpio-controller;
168                 #gpio-cells = <2>;
169         };
170
171         i2c0: i2c@58400000 {
172                 compatible = "socionext,uniphier-i2c";
173                 status = "disabled";
174                 reg = <0x58400000 0x40>;
175                 #address-cells = <1>;
176                 #size-cells = <0>;
177                 interrupts = <0 41 1>;
178                 pinctrl-names = "default";
179                 pinctrl-0 = <&pinctrl_i2c0>;
180                 clocks = <&iobus_clk>;
181                 clock-frequency = <100000>;
182         };
183
184         i2c1: i2c@58480000 {
185                 compatible = "socionext,uniphier-i2c";
186                 status = "disabled";
187                 reg = <0x58480000 0x40>;
188                 #address-cells = <1>;
189                 #size-cells = <0>;
190                 interrupts = <0 42 1>;
191                 pinctrl-names = "default";
192                 pinctrl-0 = <&pinctrl_i2c1>;
193                 clocks = <&iobus_clk>;
194                 clock-frequency = <100000>;
195         };
196
197         /* chip-internal connection for DMD */
198         i2c2: i2c@58500000 {
199                 compatible = "socionext,uniphier-i2c";
200                 reg = <0x58500000 0x40>;
201                 #address-cells = <1>;
202                 #size-cells = <0>;
203                 interrupts = <0 43 1>;
204                 pinctrl-names = "default";
205                 pinctrl-0 = <&pinctrl_i2c2>;
206                 clocks = <&iobus_clk>;
207                 clock-frequency = <400000>;
208         };
209
210         i2c3: i2c@58580000 {
211                 compatible = "socionext,uniphier-i2c";
212                 status = "disabled";
213                 reg = <0x58580000 0x40>;
214                 #address-cells = <1>;
215                 #size-cells = <0>;
216                 interrupts = <0 44 1>;
217                 pinctrl-names = "default";
218                 pinctrl-0 = <&pinctrl_i2c3>;
219                 clocks = <&iobus_clk>;
220                 clock-frequency = <100000>;
221         };
222
223         sd: sdhc@5a400000 {
224                 compatible = "socionext,uniphier-sdhc";
225                 status = "disabled";
226                 reg = <0x5a400000 0x200>;
227                 interrupts = <0 76 4>;
228                 pinctrl-names = "default", "1.8v";
229                 pinctrl-0 = <&pinctrl_sd>;
230                 pinctrl-1 = <&pinctrl_sd_1v8>;
231                 clocks = <&mio 0>;
232                 bus-width = <4>;
233         };
234
235         emmc: sdhc@5a500000 {
236                 compatible = "socionext,uniphier-sdhc";
237                 status = "disabled";
238                 reg = <0x5a500000 0x200>;
239                 interrupts = <0 78 4>;
240                 pinctrl-names = "default", "1.8v";
241                 pinctrl-0 = <&pinctrl_emmc>;
242                 pinctrl-1 = <&pinctrl_emmc_1v8>;
243                 clocks = <&mio 1>;
244                 bus-width = <8>;
245                 non-removable;
246         };
247
248         usb0: usb@5a800100 {
249                 compatible = "socionext,uniphier-ehci", "generic-ehci";
250                 status = "disabled";
251                 reg = <0x5a800100 0x100>;
252                 interrupts = <0 80 4>;
253                 pinctrl-names = "default";
254                 pinctrl-0 = <&pinctrl_usb0>;
255                 clocks = <&mio 3>, <&mio 6>;
256         };
257
258         usb1: usb@5a810100 {
259                 compatible = "socionext,uniphier-ehci", "generic-ehci";
260                 status = "disabled";
261                 reg = <0x5a810100 0x100>;
262                 interrupts = <0 81 4>;
263                 pinctrl-names = "default";
264                 pinctrl-0 = <&pinctrl_usb1>;
265                 clocks = <&mio 4>, <&mio 6>;
266         };
267
268         usb2: usb@5a820100 {
269                 compatible = "socionext,uniphier-ehci", "generic-ehci";
270                 status = "disabled";
271                 reg = <0x5a820100 0x100>;
272                 interrupts = <0 82 4>;
273                 pinctrl-names = "default";
274                 pinctrl-0 = <&pinctrl_usb2>;
275                 clocks = <&mio 5>, <&mio 6>;
276         };
277 };
278
279 &refclk {
280         clock-frequency = <24576000>;
281 };
282
283 &serial0 {
284         clock-frequency = <36864000>;
285 };
286
287 &serial1 {
288         clock-frequency = <36864000>;
289 };
290
291 &serial2 {
292         clock-frequency = <36864000>;
293 };
294
295 &serial3 {
296         interrupts = <0 29 4>;
297         clock-frequency = <36864000>;
298 };
299
300 &mio {
301         compatible = "socionext,ph1-ld4-mioctrl";
302         clock-names = "stdmac", "ehci";
303         clocks = <&sysctrl 10>, <&sysctrl 18>;
304 };
305
306 &peri {
307         compatible = "socionext,ph1-ld4-perictrl";
308         clock-names = "uart", "i2c";
309         clocks = <&sysctrl 3>, <&sysctrl 4>;
310 };
311
312 &pinctrl {
313         compatible = "socionext,ph1-ld4-pinctrl", "syscon";
314 };
315
316 &sysctrl {
317         compatible = "socionext,ph1-ld4-sysctrl";
318 };