2 * Device Tree Source for UniPhier PH1-Pro4 SoC
4 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /include/ "skeleton.dtsi"
12 compatible = "socionext,ph1-pro4";
17 enable-method = "socionext,uniphier-smp";
21 compatible = "arm,cortex-a9";
27 compatible = "arm,cortex-a9";
33 arm_timer_clk: arm_timer_clk {
35 compatible = "fixed-clock";
36 clock-frequency = <50000000>;
41 compatible = "simple-bus";
45 interrupt-parent = <&intc>;
48 compatible = "simple-bus";
53 uart0: serial@54006800 {
54 compatible = "socionext,uniphier-uart";
56 reg = <0x54006800 0x20>;
57 clock-frequency = <73728000>;
60 uart1: serial@54006900 {
61 compatible = "socionext,uniphier-uart";
63 reg = <0x54006900 0x20>;
64 clock-frequency = <73728000>;
67 uart2: serial@54006a00 {
68 compatible = "socionext,uniphier-uart";
70 reg = <0x54006a00 0x20>;
71 clock-frequency = <73728000>;
74 uart3: serial@54006b00 {
75 compatible = "socionext,uniphier-uart";
77 reg = <0x54006b00 0x20>;
78 clock-frequency = <73728000>;
82 compatible = "socionext,uniphier-fi2c";
85 reg = <0x58780000 0x80>;
86 clock-frequency = <100000>;
91 compatible = "socionext,uniphier-fi2c";
94 reg = <0x58781000 0x80>;
95 clock-frequency = <100000>;
100 compatible = "socionext,uniphier-fi2c";
101 #address-cells = <1>;
103 reg = <0x58782000 0x80>;
104 clock-frequency = <100000>;
109 compatible = "socionext,uniphier-fi2c";
110 #address-cells = <1>;
112 reg = <0x58783000 0x80>;
113 clock-frequency = <100000>;
117 /* i2c4 does not exist */
120 compatible = "socionext,uniphier-fi2c";
121 #address-cells = <1>;
123 reg = <0x58785000 0x80>;
124 clock-frequency = <400000>;
129 compatible = "socionext,uniphier-fi2c";
130 #address-cells = <1>;
132 reg = <0x58786000 0x80>;
133 clock-frequency = <400000>;
137 system-bus-controller-misc@59800000 {
138 compatible = "socionext,uniphier-system-bus-controller-misc",
140 reg = <0x59800000 0x2000>;
144 compatible = "socionext,uniphier-ehci", "generic-ehci";
146 reg = <0x5a800100 0x100>;
150 compatible = "socionext,uniphier-ehci", "generic-ehci";
152 reg = <0x5a810100 0x100>;
156 compatible = "socionext,uniphier-xhci", "generic-xhci";
158 reg = <0x65a00000 0x100>;
162 compatible = "socionext,uniphier-xhci", "generic-xhci";
164 reg = <0x65c00000 0x100>;
168 compatible = "arm,cortex-a9-global-timer";
169 reg = <0x60000200 0x20>;
170 interrupts = <1 11 0x304>;
171 clocks = <&arm_timer_clk>;
175 compatible = "arm,cortex-a9-twd-timer";
176 reg = <0x60000600 0x20>;
177 interrupts = <1 13 0x304>;
178 clocks = <&arm_timer_clk>;
181 intc: interrupt-controller@60001000 {
182 compatible = "arm,cortex-a9-gic";
183 #interrupt-cells = <3>;
184 interrupt-controller;
185 reg = <0x60001000 0x1000>,
189 nand: nand@68000000 {
190 compatible = "denali,denali-nand-dt";
191 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
192 reg-names = "nand_data", "denali_reg";