2 * Device Tree Source for UniPhier PH1-Pro5 SoC
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /include/ "uniphier-common32.dtsi"
12 compatible = "socionext,ph1-pro5";
17 enable-method = "socionext,uniphier-smp";
21 compatible = "arm,cortex-a9";
23 next-level-cache = <&l2>;
28 compatible = "arm,cortex-a9";
30 next-level-cache = <&l2>;
35 arm_timer_clk: arm_timer_clk {
37 compatible = "fixed-clock";
38 clock-frequency = <50000000>;
43 compatible = "fixed-clock";
44 clock-frequency = <73728000>;
49 compatible = "fixed-clock";
50 clock-frequency = <50000000>;
56 l2: l2-cache@500c0000 {
57 compatible = "socionext,uniphier-system-cache";
58 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
59 interrupts = <0 190 4>, <0 191 4>;
61 cache-size = <(2 * 1024 * 1024)>;
63 cache-line-size = <128>;
65 next-level-cache = <&l3>;
68 l3: l3-cache@500c8000 {
69 compatible = "socionext,uniphier-system-cache";
70 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
71 interrupts = <0 174 4>, <0 175 4>;
73 cache-size = <(2 * 1024 * 1024)>;
75 cache-line-size = <256>;
80 compatible = "socionext,uniphier-fi2c";
82 reg = <0x58780000 0x80>;
85 interrupts = <0 41 4>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_i2c0>;
89 clock-frequency = <100000>;
93 compatible = "socionext,uniphier-fi2c";
95 reg = <0x58781000 0x80>;
98 interrupts = <0 42 4>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_i2c1>;
102 clock-frequency = <100000>;
106 compatible = "socionext,uniphier-fi2c";
108 reg = <0x58782000 0x80>;
109 #address-cells = <1>;
111 interrupts = <0 43 4>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_i2c2>;
115 clock-frequency = <100000>;
119 compatible = "socionext,uniphier-fi2c";
121 reg = <0x58783000 0x80>;
122 #address-cells = <1>;
124 interrupts = <0 44 4>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_i2c3>;
128 clock-frequency = <100000>;
131 /* i2c4 does not exist */
133 /* chip-internal connection for DMD */
135 compatible = "socionext,uniphier-fi2c";
136 reg = <0x58785000 0x80>;
137 #address-cells = <1>;
139 interrupts = <0 25 4>;
141 clock-frequency = <400000>;
144 /* chip-internal connection for HDMI */
146 compatible = "socionext,uniphier-fi2c";
147 reg = <0x58786000 0x80>;
148 #address-cells = <1>;
150 interrupts = <0 26 4>;
152 clock-frequency = <400000>;
156 compatible = "socionext,uniphier-xhci", "generic-xhci";
158 reg = <0x65a00000 0x100>;
159 interrupts = <0 134 4>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_usb0>;
165 compatible = "socionext,uniphier-xhci", "generic-xhci";
167 reg = <0x65c00000 0x100>;
168 interrupts = <0 137 4>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
175 clock-frequency = <73728000>;
179 clock-frequency = <73728000>;
183 clock-frequency = <73728000>;
187 clock-frequency = <73728000>;
191 compatible = "socionext,ph1-pro5-pinctrl", "syscon";