2 * Device Tree Source for UniPhier PH1-Pro5 SoC
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /include/ "skeleton.dtsi"
12 compatible = "socionext,ph1-pro5";
17 enable-method = "socionext,uniphier-smp";
21 compatible = "arm,cortex-a9";
27 compatible = "arm,cortex-a9";
33 arm_timer_clk: arm_timer_clk {
35 compatible = "fixed-clock";
36 clock-frequency = <50000000>;
41 compatible = "fixed-clock";
42 clock-frequency = <73728000>;
47 compatible = "fixed-clock";
48 clock-frequency = <50000000>;
53 compatible = "simple-bus";
57 interrupt-parent = <&intc>;
60 compatible = "simple-bus";
65 serial0: serial@54006800 {
66 compatible = "socionext,uniphier-uart";
68 reg = <0x54006800 0x40>;
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_uart0>;
71 interrupts = <0 33 4>;
75 serial1: serial@54006900 {
76 compatible = "socionext,uniphier-uart";
78 reg = <0x54006900 0x40>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_uart1>;
81 interrupts = <0 35 4>;
85 serial2: serial@54006a00 {
86 compatible = "socionext,uniphier-uart";
88 reg = <0x54006a00 0x40>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_uart2>;
91 interrupts = <0 37 4>;
95 serial3: serial@54006b00 {
96 compatible = "socionext,uniphier-uart";
98 reg = <0x54006b00 0x40>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_uart3>;
101 interrupts = <0 177 4>;
102 clocks = <&uart_clk>;
106 compatible = "socionext,uniphier-fi2c";
108 reg = <0x58780000 0x80>;
109 #address-cells = <1>;
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_i2c0>;
113 interrupts = <0 41 4>;
115 clock-frequency = <100000>;
119 compatible = "socionext,uniphier-fi2c";
121 reg = <0x58781000 0x80>;
122 #address-cells = <1>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_i2c1>;
126 interrupts = <0 42 4>;
128 clock-frequency = <100000>;
132 compatible = "socionext,uniphier-fi2c";
134 reg = <0x58782000 0x80>;
135 #address-cells = <1>;
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_i2c2>;
139 interrupts = <0 43 4>;
141 clock-frequency = <100000>;
145 compatible = "socionext,uniphier-fi2c";
147 reg = <0x58783000 0x80>;
148 #address-cells = <1>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_i2c3>;
152 interrupts = <0 44 4>;
154 clock-frequency = <100000>;
157 /* i2c4 does not exist */
159 /* chip-internal connection for DMD */
161 compatible = "socionext,uniphier-fi2c";
162 reg = <0x58785000 0x80>;
163 #address-cells = <1>;
165 interrupts = <0 25 4>;
167 clock-frequency = <400000>;
170 /* chip-internal connection for HDMI */
172 compatible = "socionext,uniphier-fi2c";
173 reg = <0x58786000 0x80>;
174 #address-cells = <1>;
176 interrupts = <0 26 4>;
178 clock-frequency = <400000>;
181 system-bus-controller-misc@59800000 {
182 compatible = "socionext,uniphier-system-bus-controller-misc",
184 reg = <0x59800000 0x2000>;
187 pinctrl: pinctrl@5f801000 {
188 compatible = "socionext,ph1-pro5-pinctrl", "syscon";
189 reg = <0x5f801000 0xe00>;
193 compatible = "arm,cortex-a9-global-timer";
194 reg = <0x60000200 0x20>;
195 interrupts = <1 11 0x304>;
196 clocks = <&arm_timer_clk>;
200 compatible = "arm,cortex-a9-twd-timer";
201 reg = <0x60000600 0x20>;
202 interrupts = <1 13 0x304>;
203 clocks = <&arm_timer_clk>;
206 intc: interrupt-controller@60001000 {
207 compatible = "arm,cortex-a9-gic";
208 #interrupt-cells = <3>;
209 interrupt-controller;
210 reg = <0x60001000 0x1000>,
215 compatible = "socionext,uniphier-xhci", "generic-xhci";
217 reg = <0x65a00000 0x100>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_usb0>;
220 interrupts = <0 134 4>;
224 compatible = "socionext,uniphier-xhci", "generic-xhci";
226 reg = <0x65c00000 0x100>;
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
229 interrupts = <0 137 4>;
234 /include/ "uniphier-pinctrl.dtsi"