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1 /*
2  * Device Tree Source for UniPhier PH1-Pro5 SoC
3  *
4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+        X11
7  */
8
9 /include/ "uniphier-common32.dtsi"
10
11 / {
12         compatible = "socionext,ph1-pro5";
13
14         cpus {
15                 #address-cells = <1>;
16                 #size-cells = <0>;
17                 enable-method = "socionext,uniphier-smp";
18
19                 cpu@0 {
20                         device_type = "cpu";
21                         compatible = "arm,cortex-a9";
22                         reg = <0>;
23                         next-level-cache = <&l2>;
24                 };
25
26                 cpu@1 {
27                         device_type = "cpu";
28                         compatible = "arm,cortex-a9";
29                         reg = <1>;
30                         next-level-cache = <&l2>;
31                 };
32         };
33
34         clocks {
35                 arm_timer_clk: arm_timer_clk {
36                         #clock-cells = <0>;
37                         compatible = "fixed-clock";
38                         clock-frequency = <50000000>;
39                 };
40
41                 uart_clk: uart_clk {
42                         #clock-cells = <0>;
43                         compatible = "fixed-clock";
44                         clock-frequency = <73728000>;
45                 };
46
47                 i2c_clk: i2c_clk {
48                         #clock-cells = <0>;
49                         compatible = "fixed-clock";
50                         clock-frequency = <50000000>;
51                 };
52         };
53 };
54
55 &soc {
56         l2: l2-cache@500c0000 {
57                 compatible = "socionext,uniphier-system-cache";
58                 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
59                 interrupts = <0 190 4>, <0 191 4>;
60                 cache-unified;
61                 cache-size = <(2 * 1024 * 1024)>;
62                 cache-sets = <512>;
63                 cache-line-size = <128>;
64                 cache-level = <2>;
65                 next-level-cache = <&l3>;
66         };
67
68         l3: l3-cache@500c8000 {
69                 compatible = "socionext,uniphier-system-cache";
70                 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
71                 interrupts = <0 174 4>, <0 175 4>;
72                 cache-unified;
73                 cache-size = <(2 * 1024 * 1024)>;
74                 cache-sets = <512>;
75                 cache-line-size = <256>;
76                 cache-level = <3>;
77         };
78
79         port0x: gpio@55000008 {
80                 compatible = "socionext,uniphier-gpio";
81                 reg = <0x55000008 0x8>;
82                 gpio-controller;
83                 #gpio-cells = <2>;
84         };
85
86         port1x: gpio@55000010 {
87                 compatible = "socionext,uniphier-gpio";
88                 reg = <0x55000010 0x8>;
89                 gpio-controller;
90                 #gpio-cells = <2>;
91         };
92
93         port2x: gpio@55000018 {
94                 compatible = "socionext,uniphier-gpio";
95                 reg = <0x55000018 0x8>;
96                 gpio-controller;
97                 #gpio-cells = <2>;
98         };
99
100         port3x: gpio@55000020 {
101                 compatible = "socionext,uniphier-gpio";
102                 reg = <0x55000020 0x8>;
103                 gpio-controller;
104                 #gpio-cells = <2>;
105         };
106
107         port4: gpio@55000028 {
108                 compatible = "socionext,uniphier-gpio";
109                 reg = <0x55000028 0x8>;
110                 gpio-controller;
111                 #gpio-cells = <2>;
112         };
113
114         port5x: gpio@55000030 {
115                 compatible = "socionext,uniphier-gpio";
116                 reg = <0x55000030 0x8>;
117                 gpio-controller;
118                 #gpio-cells = <2>;
119         };
120
121         port6x: gpio@55000038 {
122                 compatible = "socionext,uniphier-gpio";
123                 reg = <0x55000038 0x8>;
124                 gpio-controller;
125                 #gpio-cells = <2>;
126         };
127
128         port7x: gpio@55000040 {
129                 compatible = "socionext,uniphier-gpio";
130                 reg = <0x55000040 0x8>;
131                 gpio-controller;
132                 #gpio-cells = <2>;
133         };
134
135         port8x: gpio@55000048 {
136                 compatible = "socionext,uniphier-gpio";
137                 reg = <0x55000048 0x8>;
138                 gpio-controller;
139                 #gpio-cells = <2>;
140         };
141
142         port9x: gpio@55000050 {
143                 compatible = "socionext,uniphier-gpio";
144                 reg = <0x55000050 0x8>;
145                 gpio-controller;
146                 #gpio-cells = <2>;
147         };
148
149         port10x: gpio@55000058 {
150                 compatible = "socionext,uniphier-gpio";
151                 reg = <0x55000058 0x8>;
152                 gpio-controller;
153                 #gpio-cells = <2>;
154         };
155
156         port11x: gpio@55000060 {
157                 compatible = "socionext,uniphier-gpio";
158                 reg = <0x55000060 0x8>;
159                 gpio-controller;
160                 #gpio-cells = <2>;
161         };
162
163         port12x: gpio@55000068 {
164                 compatible = "socionext,uniphier-gpio";
165                 reg = <0x55000068 0x8>;
166                 gpio-controller;
167                 #gpio-cells = <2>;
168         };
169
170         port13x: gpio@55000070 {
171                 compatible = "socionext,uniphier-gpio";
172                 reg = <0x55000070 0x8>;
173                 gpio-controller;
174                 #gpio-cells = <2>;
175         };
176
177         port14x: gpio@55000078 {
178                 compatible = "socionext,uniphier-gpio";
179                 reg = <0x55000078 0x8>;
180                 gpio-controller;
181                 #gpio-cells = <2>;
182         };
183
184         port17x: gpio@550000a0 {
185                 compatible = "socionext,uniphier-gpio";
186                 reg = <0x550000a0 0x8>;
187                 gpio-controller;
188                 #gpio-cells = <2>;
189         };
190
191         port18x: gpio@550000a8 {
192                 compatible = "socionext,uniphier-gpio";
193                 reg = <0x550000a8 0x8>;
194                 gpio-controller;
195                 #gpio-cells = <2>;
196         };
197
198         port19x: gpio@550000b0 {
199                 compatible = "socionext,uniphier-gpio";
200                 reg = <0x550000b0 0x8>;
201                 gpio-controller;
202                 #gpio-cells = <2>;
203         };
204
205         port20x: gpio@550000b8 {
206                 compatible = "socionext,uniphier-gpio";
207                 reg = <0x550000b8 0x8>;
208                 gpio-controller;
209                 #gpio-cells = <2>;
210         };
211
212         port21x: gpio@550000c0 {
213                 compatible = "socionext,uniphier-gpio";
214                 reg = <0x550000c0 0x8>;
215                 gpio-controller;
216                 #gpio-cells = <2>;
217         };
218
219         port22x: gpio@550000c8 {
220                 compatible = "socionext,uniphier-gpio";
221                 reg = <0x550000c8 0x8>;
222                 gpio-controller;
223                 #gpio-cells = <2>;
224         };
225
226         port23x: gpio@550000d0 {
227                 compatible = "socionext,uniphier-gpio";
228                 reg = <0x550000d0 0x8>;
229                 gpio-controller;
230                 #gpio-cells = <2>;
231         };
232
233         port24x: gpio@550000d8 {
234                 compatible = "socionext,uniphier-gpio";
235                 reg = <0x550000d8 0x8>;
236                 gpio-controller;
237                 #gpio-cells = <2>;
238         };
239
240         port25x: gpio@550000e0 {
241                 compatible = "socionext,uniphier-gpio";
242                 reg = <0x550000e0 0x8>;
243                 gpio-controller;
244                 #gpio-cells = <2>;
245         };
246
247         port26x: gpio@550000e8 {
248                 compatible = "socionext,uniphier-gpio";
249                 reg = <0x550000e8 0x8>;
250                 gpio-controller;
251                 #gpio-cells = <2>;
252         };
253
254         port27x: gpio@550000f0 {
255                 compatible = "socionext,uniphier-gpio";
256                 reg = <0x550000f0 0x8>;
257                 gpio-controller;
258                 #gpio-cells = <2>;
259         };
260
261         port28x: gpio@550000f8 {
262                 compatible = "socionext,uniphier-gpio";
263                 reg = <0x550000f8 0x8>;
264                 gpio-controller;
265                 #gpio-cells = <2>;
266         };
267
268         port29x: gpio@55000100 {
269                 compatible = "socionext,uniphier-gpio";
270                 reg = <0x55000100 0x8>;
271                 gpio-controller;
272                 #gpio-cells = <2>;
273         };
274
275         port30x: gpio@55000108 {
276                 compatible = "socionext,uniphier-gpio";
277                 reg = <0x55000108 0x8>;
278                 gpio-controller;
279                 #gpio-cells = <2>;
280         };
281
282         i2c0: i2c@58780000 {
283                 compatible = "socionext,uniphier-fi2c";
284                 status = "disabled";
285                 reg = <0x58780000 0x80>;
286                 #address-cells = <1>;
287                 #size-cells = <0>;
288                 interrupts = <0 41 4>;
289                 pinctrl-names = "default";
290                 pinctrl-0 = <&pinctrl_i2c0>;
291                 clocks = <&i2c_clk>;
292                 clock-frequency = <100000>;
293         };
294
295         i2c1: i2c@58781000 {
296                 compatible = "socionext,uniphier-fi2c";
297                 status = "disabled";
298                 reg = <0x58781000 0x80>;
299                 #address-cells = <1>;
300                 #size-cells = <0>;
301                 interrupts = <0 42 4>;
302                 pinctrl-names = "default";
303                 pinctrl-0 = <&pinctrl_i2c1>;
304                 clocks = <&i2c_clk>;
305                 clock-frequency = <100000>;
306         };
307
308         i2c2: i2c@58782000 {
309                 compatible = "socionext,uniphier-fi2c";
310                 status = "disabled";
311                 reg = <0x58782000 0x80>;
312                 #address-cells = <1>;
313                 #size-cells = <0>;
314                 interrupts = <0 43 4>;
315                 pinctrl-names = "default";
316                 pinctrl-0 = <&pinctrl_i2c2>;
317                 clocks = <&i2c_clk>;
318                 clock-frequency = <100000>;
319         };
320
321         i2c3: i2c@58783000 {
322                 compatible = "socionext,uniphier-fi2c";
323                 status = "disabled";
324                 reg = <0x58783000 0x80>;
325                 #address-cells = <1>;
326                 #size-cells = <0>;
327                 interrupts = <0 44 4>;
328                 pinctrl-names = "default";
329                 pinctrl-0 = <&pinctrl_i2c3>;
330                 clocks = <&i2c_clk>;
331                 clock-frequency = <100000>;
332         };
333
334         /* i2c4 does not exist */
335
336         /* chip-internal connection for DMD */
337         i2c5: i2c@58785000 {
338                 compatible = "socionext,uniphier-fi2c";
339                 reg = <0x58785000 0x80>;
340                 #address-cells = <1>;
341                 #size-cells = <0>;
342                 interrupts = <0 25 4>;
343                 clocks = <&i2c_clk>;
344                 clock-frequency = <400000>;
345         };
346
347         /* chip-internal connection for HDMI */
348         i2c6: i2c@58786000 {
349                 compatible = "socionext,uniphier-fi2c";
350                 reg = <0x58786000 0x80>;
351                 #address-cells = <1>;
352                 #size-cells = <0>;
353                 interrupts = <0 26 4>;
354                 clocks = <&i2c_clk>;
355                 clock-frequency = <400000>;
356         };
357
358         emmc: sdhc@68400000 {
359                 compatible = "socionext,uniphier-sdhc";
360                 status = "disabled";
361                 reg = <0x68400000 0x800>;
362                 interrupts = <0 78 4>;
363                 pinctrl-names = "default";
364                 pinctrl-0 = <&pinctrl_emmc>;
365                 clocks = <&mio 1>;
366                 bus-width = <8>;
367                 non-removable;
368         };
369
370         sd: sdhc@68800000 {
371                 compatible = "socionext,uniphier-sdhc";
372                 status = "disabled";
373                 reg = <0x68800000 0x800>;
374                 interrupts = <0 76 4>;
375                 pinctrl-names = "default", "1.8v";
376                 pinctrl-0 = <&pinctrl_sd>;
377                 pinctrl-1 = <&pinctrl_sd_1v8>;
378                 clocks = <&mio 0>;
379                 bus-width = <4>;
380         };
381
382         usb0: usb@65a00000 {
383                 compatible = "socionext,uniphier-xhci", "generic-xhci";
384                 status = "disabled";
385                 reg = <0x65a00000 0x100>;
386                 interrupts = <0 134 4>;
387                 pinctrl-names = "default";
388                 pinctrl-0 = <&pinctrl_usb0>;
389         };
390
391         usb1: usb@65c00000 {
392                 compatible = "socionext,uniphier-xhci", "generic-xhci";
393                 status = "disabled";
394                 reg = <0x65c00000 0x100>;
395                 interrupts = <0 137 4>;
396                 pinctrl-names = "default";
397                 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
398         };
399 };
400
401 &refclk {
402         clock-frequency = <20000000>;
403 };
404
405 &serial0 {
406         clock-frequency = <73728000>;
407 };
408
409 &serial1 {
410         clock-frequency = <73728000>;
411 };
412
413 &serial2 {
414         clock-frequency = <73728000>;
415 };
416
417 &serial3 {
418         clock-frequency = <73728000>;
419 };
420
421 &mio {
422         compatible = "socionext,ph1-pro5-mioctrl";
423         clock-names = "stdmac";
424         clocks = <&sysctrl 10>;
425 };
426
427 &peri {
428         compatible = "socionext,ph1-pro5-perictrl";
429         clock-names = "uart", "fi2c";
430         clocks = <&sysctrl 3>, <&sysctrl 4>;
431 };
432
433 &pinctrl {
434         compatible = "socionext,ph1-pro5-pinctrl", "syscon";
435 };
436
437 &sysctrl {
438         compatible = "socionext,ph1-pro5-sysctrl";
439 };