2 * Device Tree Source for UniPhier PH1-Pro5 SoC
4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /include/ "uniphier-common32.dtsi"
12 compatible = "socionext,ph1-pro5";
17 enable-method = "socionext,uniphier-smp";
21 compatible = "arm,cortex-a9";
23 next-level-cache = <&l2>;
28 compatible = "arm,cortex-a9";
30 next-level-cache = <&l2>;
35 arm_timer_clk: arm_timer_clk {
37 compatible = "fixed-clock";
38 clock-frequency = <50000000>;
43 compatible = "fixed-clock";
44 clock-frequency = <50000000>;
50 l2: l2-cache@500c0000 {
51 compatible = "socionext,uniphier-system-cache";
52 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
53 interrupts = <0 190 4>, <0 191 4>;
55 cache-size = <(2 * 1024 * 1024)>;
57 cache-line-size = <128>;
59 next-level-cache = <&l3>;
62 l3: l3-cache@500c8000 {
63 compatible = "socionext,uniphier-system-cache";
64 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
65 interrupts = <0 174 4>, <0 175 4>;
67 cache-size = <(2 * 1024 * 1024)>;
69 cache-line-size = <256>;
73 port0x: gpio@55000008 {
74 compatible = "socionext,uniphier-gpio";
75 reg = <0x55000008 0x8>;
80 port1x: gpio@55000010 {
81 compatible = "socionext,uniphier-gpio";
82 reg = <0x55000010 0x8>;
87 port2x: gpio@55000018 {
88 compatible = "socionext,uniphier-gpio";
89 reg = <0x55000018 0x8>;
94 port3x: gpio@55000020 {
95 compatible = "socionext,uniphier-gpio";
96 reg = <0x55000020 0x8>;
101 port4: gpio@55000028 {
102 compatible = "socionext,uniphier-gpio";
103 reg = <0x55000028 0x8>;
108 port5x: gpio@55000030 {
109 compatible = "socionext,uniphier-gpio";
110 reg = <0x55000030 0x8>;
115 port6x: gpio@55000038 {
116 compatible = "socionext,uniphier-gpio";
117 reg = <0x55000038 0x8>;
122 port7x: gpio@55000040 {
123 compatible = "socionext,uniphier-gpio";
124 reg = <0x55000040 0x8>;
129 port8x: gpio@55000048 {
130 compatible = "socionext,uniphier-gpio";
131 reg = <0x55000048 0x8>;
136 port9x: gpio@55000050 {
137 compatible = "socionext,uniphier-gpio";
138 reg = <0x55000050 0x8>;
143 port10x: gpio@55000058 {
144 compatible = "socionext,uniphier-gpio";
145 reg = <0x55000058 0x8>;
150 port11x: gpio@55000060 {
151 compatible = "socionext,uniphier-gpio";
152 reg = <0x55000060 0x8>;
157 port12x: gpio@55000068 {
158 compatible = "socionext,uniphier-gpio";
159 reg = <0x55000068 0x8>;
164 port13x: gpio@55000070 {
165 compatible = "socionext,uniphier-gpio";
166 reg = <0x55000070 0x8>;
171 port14x: gpio@55000078 {
172 compatible = "socionext,uniphier-gpio";
173 reg = <0x55000078 0x8>;
178 port17x: gpio@550000a0 {
179 compatible = "socionext,uniphier-gpio";
180 reg = <0x550000a0 0x8>;
185 port18x: gpio@550000a8 {
186 compatible = "socionext,uniphier-gpio";
187 reg = <0x550000a8 0x8>;
192 port19x: gpio@550000b0 {
193 compatible = "socionext,uniphier-gpio";
194 reg = <0x550000b0 0x8>;
199 port20x: gpio@550000b8 {
200 compatible = "socionext,uniphier-gpio";
201 reg = <0x550000b8 0x8>;
206 port21x: gpio@550000c0 {
207 compatible = "socionext,uniphier-gpio";
208 reg = <0x550000c0 0x8>;
213 port22x: gpio@550000c8 {
214 compatible = "socionext,uniphier-gpio";
215 reg = <0x550000c8 0x8>;
220 port23x: gpio@550000d0 {
221 compatible = "socionext,uniphier-gpio";
222 reg = <0x550000d0 0x8>;
227 port24x: gpio@550000d8 {
228 compatible = "socionext,uniphier-gpio";
229 reg = <0x550000d8 0x8>;
234 port25x: gpio@550000e0 {
235 compatible = "socionext,uniphier-gpio";
236 reg = <0x550000e0 0x8>;
241 port26x: gpio@550000e8 {
242 compatible = "socionext,uniphier-gpio";
243 reg = <0x550000e8 0x8>;
248 port27x: gpio@550000f0 {
249 compatible = "socionext,uniphier-gpio";
250 reg = <0x550000f0 0x8>;
255 port28x: gpio@550000f8 {
256 compatible = "socionext,uniphier-gpio";
257 reg = <0x550000f8 0x8>;
262 port29x: gpio@55000100 {
263 compatible = "socionext,uniphier-gpio";
264 reg = <0x55000100 0x8>;
269 port30x: gpio@55000108 {
270 compatible = "socionext,uniphier-gpio";
271 reg = <0x55000108 0x8>;
277 compatible = "socionext,uniphier-fi2c";
279 reg = <0x58780000 0x80>;
280 #address-cells = <1>;
282 interrupts = <0 41 4>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_i2c0>;
286 clock-frequency = <100000>;
290 compatible = "socionext,uniphier-fi2c";
292 reg = <0x58781000 0x80>;
293 #address-cells = <1>;
295 interrupts = <0 42 4>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_i2c1>;
299 clock-frequency = <100000>;
303 compatible = "socionext,uniphier-fi2c";
305 reg = <0x58782000 0x80>;
306 #address-cells = <1>;
308 interrupts = <0 43 4>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_i2c2>;
312 clock-frequency = <100000>;
316 compatible = "socionext,uniphier-fi2c";
318 reg = <0x58783000 0x80>;
319 #address-cells = <1>;
321 interrupts = <0 44 4>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&pinctrl_i2c3>;
325 clock-frequency = <100000>;
328 /* i2c4 does not exist */
330 /* chip-internal connection for DMD */
332 compatible = "socionext,uniphier-fi2c";
333 reg = <0x58785000 0x80>;
334 #address-cells = <1>;
336 interrupts = <0 25 4>;
338 clock-frequency = <400000>;
341 /* chip-internal connection for HDMI */
343 compatible = "socionext,uniphier-fi2c";
344 reg = <0x58786000 0x80>;
345 #address-cells = <1>;
347 interrupts = <0 26 4>;
349 clock-frequency = <400000>;
353 compatible = "simple-mfd", "syscon";
354 reg = <0x5fc20000 0x200>;
357 emmc: sdhc@68400000 {
358 compatible = "socionext,uniphier-sdhc";
360 reg = <0x68400000 0x800>;
361 interrupts = <0 78 4>;
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_emmc>;
364 clocks = <&mio_clk 1>;
370 compatible = "socionext,uniphier-sdhc";
372 reg = <0x68800000 0x800>;
373 interrupts = <0 76 4>;
374 pinctrl-names = "default", "1.8v";
375 pinctrl-0 = <&pinctrl_sd>;
376 pinctrl-1 = <&pinctrl_sd_1v8>;
377 clocks = <&mio_clk 0>;
382 compatible = "socionext,uniphier-xhci", "generic-xhci";
384 reg = <0x65a00000 0x100>;
385 interrupts = <0 134 4>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_usb0>;
391 compatible = "socionext,uniphier-xhci", "generic-xhci";
393 reg = <0x65c00000 0x100>;
394 interrupts = <0 137 4>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
401 clock-frequency = <20000000>;
405 clock-frequency = <73728000>;
409 clock-frequency = <73728000>;
413 clock-frequency = <73728000>;
417 clock-frequency = <73728000>;
421 compatible = "socionext,uniphier-pro5-mio-clock";
425 compatible = "socionext,uniphier-pro5-mio-reset";
429 compatible = "socionext,uniphier-pro5-peri-clock";
433 compatible = "socionext,uniphier-pro5-peri-reset";
437 compatible = "socionext,uniphier-pro5-pinctrl";
441 compatible = "socionext,uniphier-pro5-clock";
445 compatible = "socionext,uniphier-pro5-reset";