git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-ph1-pro5.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-Pro5 SoC
   3  *
   4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /include/ "uniphier-common32.dtsi"
  10
  11 / {
  12         compatible = "socionext,ph1-pro5";
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17                 enable-method = "socionext,uniphier-smp";
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                 };
  24
  25                 cpu@1 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         reg = <1>;
  29                 };
  30         };
  31
  32         clocks {
  33                 arm_timer_clk: arm_timer_clk {
  34                         #clock-cells = <0>;
  35                         compatible = "fixed-clock";
  36                         clock-frequency = <50000000>;
  37                 };
  38
  39                 uart_clk: uart_clk {
  40                         #clock-cells = <0>;
  41                         compatible = "fixed-clock";
  42                         clock-frequency = <73728000>;
  43                 };
  44
  45                 i2c_clk: i2c_clk {
  46                         #clock-cells = <0>;
  47                         compatible = "fixed-clock";
  48                         clock-frequency = <50000000>;
  49                 };
  50         };
  51 };
  52
  53 &soc {
  54         i2c0: i2c@58780000 {
  55                 compatible = "socionext,uniphier-fi2c";
  56                 status = "disabled";
  57                 reg = <0x58780000 0x80>;
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60                 interrupts = <0 41 4>;
  61                 pinctrl-names = "default";
  62                 pinctrl-0 = <&pinctrl_i2c0>;
  63                 clocks = <&i2c_clk>;
  64                 clock-frequency = <100000>;
  65         };
  66
  67         i2c1: i2c@58781000 {
  68                 compatible = "socionext,uniphier-fi2c";
  69                 status = "disabled";
  70                 reg = <0x58781000 0x80>;
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73                 interrupts = <0 42 4>;
  74                 pinctrl-names = "default";
  75                 pinctrl-0 = <&pinctrl_i2c1>;
  76                 clocks = <&i2c_clk>;
  77                 clock-frequency = <100000>;
  78         };
  79
  80         i2c2: i2c@58782000 {
  81                 compatible = "socionext,uniphier-fi2c";
  82                 status = "disabled";
  83                 reg = <0x58782000 0x80>;
  84                 #address-cells = <1>;
  85                 #size-cells = <0>;
  86                 interrupts = <0 43 4>;
  87                 pinctrl-names = "default";
  88                 pinctrl-0 = <&pinctrl_i2c2>;
  89                 clocks = <&i2c_clk>;
  90                 clock-frequency = <100000>;
  91         };
  92
  93         i2c3: i2c@58783000 {
  94                 compatible = "socionext,uniphier-fi2c";
  95                 status = "disabled";
  96                 reg = <0x58783000 0x80>;
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99                 interrupts = <0 44 4>;
 100                 pinctrl-names = "default";
 101                 pinctrl-0 = <&pinctrl_i2c3>;
 102                 clocks = <&i2c_clk>;
 103                 clock-frequency = <100000>;
 104         };
 105
 106         /* i2c4 does not exist */
 107
 108         /* chip-internal connection for DMD */
 109         i2c5: i2c@58785000 {
 110                 compatible = "socionext,uniphier-fi2c";
 111                 reg = <0x58785000 0x80>;
 112                 #address-cells = <1>;
 113                 #size-cells = <0>;
 114                 interrupts = <0 25 4>;
 115                 clocks = <&i2c_clk>;
 116                 clock-frequency = <400000>;
 117         };
 118
 119         /* chip-internal connection for HDMI */
 120         i2c6: i2c@58786000 {
 121                 compatible = "socionext,uniphier-fi2c";
 122                 reg = <0x58786000 0x80>;
 123                 #address-cells = <1>;
 124                 #size-cells = <0>;
 125                 interrupts = <0 26 4>;
 126                 clocks = <&i2c_clk>;
 127                 clock-frequency = <400000>;
 128         };
 129
 130         usb0: usb@65a00000 {
 131                 compatible = "socionext,uniphier-xhci", "generic-xhci";
 132                 status = "disabled";
 133                 reg = <0x65a00000 0x100>;
 134                 pinctrl-names = "default";
 135                 pinctrl-0 = <&pinctrl_usb0>;
 136                 interrupts = <0 134 4>;
 137         };
 138
 139         usb1: usb@65c00000 {
 140                 compatible = "socionext,uniphier-xhci", "generic-xhci";
 141                 status = "disabled";
 142                 reg = <0x65c00000 0x100>;
 143                 pinctrl-names = "default";
 144                 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
 145                 interrupts = <0 137 4>;
 146         };
 147 };
 148
 149 &serial0 {
 150         clock-frequency = <73728000>;
 151 };
 152
 153 &serial1 {
 154         clock-frequency = <73728000>;
 155 };
 156
 157 &serial2 {
 158         clock-frequency = <73728000>;
 159 };
 160
 161 &serial3 {
 162         clock-frequency = <73728000>;
 163 };
 164
 165 &pinctrl {
 166         compatible = "socionext,ph1-pro5-pinctrl", "syscon";
 167 };