git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-ph1-sld3.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-sLD3 SoC
   3  *
   4  * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         compatible = "socionext,ph1-sld3";
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17                 enable-method = "socionext,uniphier-smp";
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                 };
  24
  25                 cpu@1 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         reg = <1>;
  29                 };
  30         };
  31
  32         clocks {
  33                 refclk: ref {
  34                         #clock-cells = <0>;
  35                         compatible = "fixed-clock";
  36                         clock-frequency = <24576000>;
  37                 };
  38
  39                 arm_timer_clk: arm_timer_clk {
  40                         #clock-cells = <0>;
  41                         compatible = "fixed-clock";
  42                         clock-frequency = <50000000>;
  43                 };
  44
  45                 uart_clk: uart_clk {
  46                         #clock-cells = <0>;
  47                         compatible = "fixed-clock";
  48                         clock-frequency = <36864000>;
  49                 };
  50
  51                 iobus_clk: iobus_clk {
  52                         #clock-cells = <0>;
  53                         compatible = "fixed-clock";
  54                         clock-frequency = <100000000>;
  55                 };
  56         };
  57
  58         soc {
  59                 compatible = "simple-bus";
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 ranges;
  63                 interrupt-parent = <&intc>;
  64                 u-boot,dm-pre-reloc;
  65
  66                 timer@20000200 {
  67                         compatible = "arm,cortex-a9-global-timer";
  68                         reg = <0x20000200 0x20>;
  69                         interrupts = <1 11 0x304>;
  70                         clocks = <&arm_timer_clk>;
  71                 };
  72
  73                 timer@20000600 {
  74                         compatible = "arm,cortex-a9-twd-timer";
  75                         reg = <0x20000600 0x20>;
  76                         interrupts = <1 13 0x304>;
  77                         clocks = <&arm_timer_clk>;
  78                 };
  79
  80                 intc: interrupt-controller@20001000 {
  81                         compatible = "arm,cortex-a9-gic";
  82                         #interrupt-cells = <3>;
  83                         interrupt-controller;
  84                         reg = <0x20001000 0x1000>,
  85                               <0x20000100 0x100>;
  86                 };
  87
  88                 serial0: serial@54006800 {
  89                         compatible = "socionext,uniphier-uart";
  90                         status = "disabled";
  91                         reg = <0x54006800 0x40>;
  92                         interrupts = <0 33 4>;
  93                         clocks = <&uart_clk>;
  94                         clock-frequency = <36864000>;
  95                 };
  96
  97                 serial1: serial@54006900 {
  98                         compatible = "socionext,uniphier-uart";
  99                         status = "disabled";
 100                         reg = <0x54006900 0x40>;
 101                         interrupts = <0 35 4>;
 102                         clocks = <&uart_clk>;
 103                         clock-frequency = <36864000>;
 104                 };
 105
 106                 serial2: serial@54006a00 {
 107                         compatible = "socionext,uniphier-uart";
 108                         status = "disabled";
 109                         reg = <0x54006a00 0x40>;
 110                         interrupts = <0 37 4>;
 111                         clocks = <&uart_clk>;
 112                         clock-frequency = <36864000>;
 113                 };
 114
 115                 port0x: gpio@55000008 {
 116                         compatible = "socionext,uniphier-gpio";
 117                         reg = <0x55000008 0x8>;
 118                         gpio-controller;
 119                         #gpio-cells = <2>;
 120                 };
 121
 122                 port1x: gpio@55000010 {
 123                         compatible = "socionext,uniphier-gpio";
 124                         reg = <0x55000010 0x8>;
 125                         gpio-controller;
 126                         #gpio-cells = <2>;
 127                 };
 128
 129                 port2x: gpio@55000018 {
 130                         compatible = "socionext,uniphier-gpio";
 131                         reg = <0x55000018 0x8>;
 132                         gpio-controller;
 133                         #gpio-cells = <2>;
 134                 };
 135
 136                 port3x: gpio@55000020 {
 137                         compatible = "socionext,uniphier-gpio";
 138                         reg = <0x55000020 0x8>;
 139                         gpio-controller;
 140                         #gpio-cells = <2>;
 141                 };
 142
 143                 port4: gpio@55000028 {
 144                         compatible = "socionext,uniphier-gpio";
 145                         reg = <0x55000028 0x8>;
 146                         gpio-controller;
 147                         #gpio-cells = <2>;
 148                 };
 149
 150                 port5x: gpio@55000030 {
 151                         compatible = "socionext,uniphier-gpio";
 152                         reg = <0x55000030 0x8>;
 153                         gpio-controller;
 154                         #gpio-cells = <2>;
 155                 };
 156
 157                 port6x: gpio@55000038 {
 158                         compatible = "socionext,uniphier-gpio";
 159                         reg = <0x55000038 0x8>;
 160                         gpio-controller;
 161                         #gpio-cells = <2>;
 162                 };
 163
 164                 port7x: gpio@55000040 {
 165                         compatible = "socionext,uniphier-gpio";
 166                         reg = <0x55000040 0x8>;
 167                         gpio-controller;
 168                         #gpio-cells = <2>;
 169                 };
 170
 171                 port8x: gpio@55000048 {
 172                         compatible = "socionext,uniphier-gpio";
 173                         reg = <0x55000048 0x8>;
 174                         gpio-controller;
 175                         #gpio-cells = <2>;
 176                 };
 177
 178                 port9x: gpio@55000050 {
 179                         compatible = "socionext,uniphier-gpio";
 180                         reg = <0x55000050 0x8>;
 181                         gpio-controller;
 182                         #gpio-cells = <2>;
 183                 };
 184
 185                 port10x: gpio@55000058 {
 186                         compatible = "socionext,uniphier-gpio";
 187                         reg = <0x55000058 0x8>;
 188                         gpio-controller;
 189                         #gpio-cells = <2>;
 190                 };
 191
 192                 port11x: gpio@55000060 {
 193                         compatible = "socionext,uniphier-gpio";
 194                         reg = <0x55000060 0x8>;
 195                         gpio-controller;
 196                         #gpio-cells = <2>;
 197                 };
 198
 199                 port12x: gpio@55000068 {
 200                         compatible = "socionext,uniphier-gpio";
 201                         reg = <0x55000068 0x8>;
 202                         gpio-controller;
 203                         #gpio-cells = <2>;
 204                 };
 205
 206                 port13x: gpio@55000070 {
 207                         compatible = "socionext,uniphier-gpio";
 208                         reg = <0x55000070 0x8>;
 209                         gpio-controller;
 210                         #gpio-cells = <2>;
 211                 };
 212
 213                 port14x: gpio@55000078 {
 214                         compatible = "socionext,uniphier-gpio";
 215                         reg = <0x55000078 0x8>;
 216                         gpio-controller;
 217                         #gpio-cells = <2>;
 218                 };
 219
 220                 port16x: gpio@55000088 {
 221                         compatible = "socionext,uniphier-gpio";
 222                         reg = <0x55000088 0x8>;
 223                         gpio-controller;
 224                         #gpio-cells = <2>;
 225                 };
 226
 227                 i2c0: i2c@58400000 {
 228                         compatible = "socionext,uniphier-i2c";
 229                         status = "disabled";
 230                         reg = <0x58400000 0x40>;
 231                         #address-cells = <1>;
 232                         #size-cells = <0>;
 233                         interrupts = <0 41 1>;
 234                         clocks = <&iobus_clk>;
 235                         clock-frequency = <100000>;
 236                 };
 237
 238                 i2c1: i2c@58480000 {
 239                         compatible = "socionext,uniphier-i2c";
 240                         status = "disabled";
 241                         reg = <0x58480000 0x40>;
 242                         #address-cells = <1>;
 243                         #size-cells = <0>;
 244                         interrupts = <0 42 1>;
 245                         clocks = <&iobus_clk>;
 246                         clock-frequency = <100000>;
 247                 };
 248
 249                 i2c2: i2c@58500000 {
 250                         compatible = "socionext,uniphier-i2c";
 251                         status = "disabled";
 252                         reg = <0x58500000 0x40>;
 253                         #address-cells = <1>;
 254                         #size-cells = <0>;
 255                         interrupts = <0 43 1>;
 256                         clocks = <&iobus_clk>;
 257                         clock-frequency = <100000>;
 258                 };
 259
 260                 i2c3: i2c@58580000 {
 261                         compatible = "socionext,uniphier-i2c";
 262                         status = "disabled";
 263                         reg = <0x58580000 0x40>;
 264                         #address-cells = <1>;
 265                         #size-cells = <0>;
 266                         interrupts = <0 44 1>;
 267                         clocks = <&iobus_clk>;
 268                         clock-frequency = <100000>;
 269                 };
 270
 271                 /* chip-internal connection for DMD */
 272                 i2c4: i2c@58600000 {
 273                         compatible = "socionext,uniphier-i2c";
 274                         reg = <0x58600000 0x40>;
 275                         #address-cells = <1>;
 276                         #size-cells = <0>;
 277                         interrupts = <0 45 1>;
 278                         clocks = <&iobus_clk>;
 279                         clock-frequency = <400000>;
 280                 };
 281
 282                 system_bus: system-bus@58c00000 {
 283                         compatible = "socionext,uniphier-system-bus";
 284                         reg = <0x58c00000 0x400>;
 285                         #address-cells = <2>;
 286                         #size-cells = <1>;
 287                 };
 288
 289                 smpctrl@59800000 {
 290                         compatible = "socionext,uniphier-smpctrl";
 291                         reg = <0x59801000 0x400>;
 292                 };
 293
 294                 mio: mioctrl@59810000 {
 295                         compatible = "socionext,ph1-sld3-mioctrl";
 296                         reg = <0x59810000 0x800>;
 297                         #clock-cells = <1>;
 298                         clock-names = "stdmac", "ehci";
 299                         clocks = <&sysctrl 10>, <&sysctrl 18>;
 300                 };
 301
 302                 emmc: sdhc@5a400000 {
 303                         compatible = "socionext,uniphier-sdhc";
 304                         status = "disabled";
 305                         reg = <0x5a400000 0x200>;
 306                         interrupts = <0 78 4>;
 307                         clocks = <&mio 1>;
 308                         bus-width = <8>;
 309                         non-removable;
 310                 };
 311
 312                 sd: sdhc@5a500000 {
 313                         compatible = "socionext,uniphier-sdhc";
 314                         status = "disabled";
 315                         reg = <0x5a500000 0x200>;
 316                         interrupts = <0 76 4>;
 317                         clocks = <&mio 0>;
 318                         bus-width = <4>;
 319                 };
 320
 321                 usb0: usb@5a800100 {
 322                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 323                         status = "disabled";
 324                         reg = <0x5a800100 0x100>;
 325                         interrupts = <0 80 4>;
 326                         clocks = <&mio 3>, <&mio 6>;
 327                 };
 328
 329                 usb1: usb@5a810100 {
 330                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 331                         status = "disabled";
 332                         reg = <0x5a810100 0x100>;
 333                         interrupts = <0 81 4>;
 334                         clocks = <&mio 4>, <&mio 6>;
 335                 };
 336
 337                 usb2: usb@5a820100 {
 338                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 339                         status = "disabled";
 340                         reg = <0x5a820100 0x100>;
 341                         interrupts = <0 82 4>;
 342                         clocks = <&mio 5>, <&mio 6>;
 343                 };
 344
 345                 usb3: usb@5a830100 {
 346                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 347                         status = "disabled";
 348                         reg = <0x5a830100 0x100>;
 349                         interrupts = <0 83 4>;
 350                         clocks = <&mio 7>, <&mio 6>;
 351                 };
 352
 353                 aidet@f1830000 {
 354                         compatible = "simple-mfd", "syscon";
 355                         reg = <0xf1830000 0x200>;
 356                 };
 357
 358                 sysctrl: sysctrl@f1840000 {
 359                         compatible = "socionext,ph1-sld3-sysctrl";
 360                         reg = <0xf1840000 0x4000>;
 361                         #clock-cells = <1>;
 362                         clock-names = "ref";
 363                         clocks = <&refclk>;
 364                 };
 365
 366                 nand: nand@f8000000 {
 367                         compatible = "denali,denali-nand-dt";
 368                         reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
 369                         reg-names = "nand_data", "denali_reg";
 370                 };
 371         };
 372 };