2 * Device Tree Source for UniPhier PH1-sLD3 SoC
4 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /include/ "skeleton.dtsi"
12 compatible = "socionext,ph1-sld3";
17 enable-method = "socionext,uniphier-smp";
21 compatible = "arm,cortex-a9";
27 compatible = "arm,cortex-a9";
35 compatible = "fixed-clock";
36 clock-frequency = <24576000>;
39 arm_timer_clk: arm_timer_clk {
41 compatible = "fixed-clock";
42 clock-frequency = <50000000>;
47 compatible = "fixed-clock";
48 clock-frequency = <36864000>;
51 iobus_clk: iobus_clk {
53 compatible = "fixed-clock";
54 clock-frequency = <100000000>;
59 compatible = "simple-bus";
63 interrupt-parent = <&intc>;
67 compatible = "arm,cortex-a9-global-timer";
68 reg = <0x20000200 0x20>;
69 interrupts = <1 11 0x304>;
70 clocks = <&arm_timer_clk>;
74 compatible = "arm,cortex-a9-twd-timer";
75 reg = <0x20000600 0x20>;
76 interrupts = <1 13 0x304>;
77 clocks = <&arm_timer_clk>;
80 intc: interrupt-controller@20001000 {
81 compatible = "arm,cortex-a9-gic";
82 #interrupt-cells = <3>;
84 reg = <0x20001000 0x1000>,
88 serial0: serial@54006800 {
89 compatible = "socionext,uniphier-uart";
91 reg = <0x54006800 0x40>;
92 interrupts = <0 33 4>;
94 clock-frequency = <36864000>;
97 serial1: serial@54006900 {
98 compatible = "socionext,uniphier-uart";
100 reg = <0x54006900 0x40>;
101 interrupts = <0 35 4>;
102 clocks = <&uart_clk>;
103 clock-frequency = <36864000>;
106 serial2: serial@54006a00 {
107 compatible = "socionext,uniphier-uart";
109 reg = <0x54006a00 0x40>;
110 interrupts = <0 37 4>;
111 clocks = <&uart_clk>;
112 clock-frequency = <36864000>;
115 port0x: gpio@55000008 {
116 compatible = "socionext,uniphier-gpio";
117 reg = <0x55000008 0x8>;
122 port1x: gpio@55000010 {
123 compatible = "socionext,uniphier-gpio";
124 reg = <0x55000010 0x8>;
129 port2x: gpio@55000018 {
130 compatible = "socionext,uniphier-gpio";
131 reg = <0x55000018 0x8>;
136 port3x: gpio@55000020 {
137 compatible = "socionext,uniphier-gpio";
138 reg = <0x55000020 0x8>;
143 port4: gpio@55000028 {
144 compatible = "socionext,uniphier-gpio";
145 reg = <0x55000028 0x8>;
150 port5x: gpio@55000030 {
151 compatible = "socionext,uniphier-gpio";
152 reg = <0x55000030 0x8>;
157 port6x: gpio@55000038 {
158 compatible = "socionext,uniphier-gpio";
159 reg = <0x55000038 0x8>;
164 port7x: gpio@55000040 {
165 compatible = "socionext,uniphier-gpio";
166 reg = <0x55000040 0x8>;
171 port8x: gpio@55000048 {
172 compatible = "socionext,uniphier-gpio";
173 reg = <0x55000048 0x8>;
178 port9x: gpio@55000050 {
179 compatible = "socionext,uniphier-gpio";
180 reg = <0x55000050 0x8>;
185 port10x: gpio@55000058 {
186 compatible = "socionext,uniphier-gpio";
187 reg = <0x55000058 0x8>;
192 port11x: gpio@55000060 {
193 compatible = "socionext,uniphier-gpio";
194 reg = <0x55000060 0x8>;
199 port12x: gpio@55000068 {
200 compatible = "socionext,uniphier-gpio";
201 reg = <0x55000068 0x8>;
206 port13x: gpio@55000070 {
207 compatible = "socionext,uniphier-gpio";
208 reg = <0x55000070 0x8>;
213 port14x: gpio@55000078 {
214 compatible = "socionext,uniphier-gpio";
215 reg = <0x55000078 0x8>;
220 port16x: gpio@55000088 {
221 compatible = "socionext,uniphier-gpio";
222 reg = <0x55000088 0x8>;
228 compatible = "socionext,uniphier-i2c";
230 reg = <0x58400000 0x40>;
231 #address-cells = <1>;
233 interrupts = <0 41 1>;
234 clocks = <&iobus_clk>;
235 clock-frequency = <100000>;
239 compatible = "socionext,uniphier-i2c";
241 reg = <0x58480000 0x40>;
242 #address-cells = <1>;
244 interrupts = <0 42 1>;
245 clocks = <&iobus_clk>;
246 clock-frequency = <100000>;
250 compatible = "socionext,uniphier-i2c";
252 reg = <0x58500000 0x40>;
253 #address-cells = <1>;
255 interrupts = <0 43 1>;
256 clocks = <&iobus_clk>;
257 clock-frequency = <100000>;
261 compatible = "socionext,uniphier-i2c";
263 reg = <0x58580000 0x40>;
264 #address-cells = <1>;
266 interrupts = <0 44 1>;
267 clocks = <&iobus_clk>;
268 clock-frequency = <100000>;
271 /* chip-internal connection for DMD */
273 compatible = "socionext,uniphier-i2c";
274 reg = <0x58600000 0x40>;
275 #address-cells = <1>;
277 interrupts = <0 45 1>;
278 clocks = <&iobus_clk>;
279 clock-frequency = <400000>;
282 system_bus: system-bus@58c00000 {
283 compatible = "socionext,uniphier-system-bus";
284 reg = <0x58c00000 0x400>;
285 #address-cells = <2>;
290 compatible = "socionext,uniphier-smpctrl";
291 reg = <0x59801000 0x400>;
294 mio: mioctrl@59810000 {
295 compatible = "socionext,ph1-sld3-mioctrl";
296 reg = <0x59810000 0x800>;
298 clock-names = "stdmac", "ehci";
299 clocks = <&sysctrl 10>, <&sysctrl 18>;
302 emmc: sdhc@5a400000 {
303 compatible = "socionext,uniphier-sdhc";
305 reg = <0x5a400000 0x200>;
306 interrupts = <0 78 4>;
313 compatible = "socionext,uniphier-sdhc";
315 reg = <0x5a500000 0x200>;
316 interrupts = <0 76 4>;
322 compatible = "socionext,uniphier-ehci", "generic-ehci";
324 reg = <0x5a800100 0x100>;
325 interrupts = <0 80 4>;
326 clocks = <&mio 3>, <&mio 6>;
330 compatible = "socionext,uniphier-ehci", "generic-ehci";
332 reg = <0x5a810100 0x100>;
333 interrupts = <0 81 4>;
334 clocks = <&mio 4>, <&mio 6>;
338 compatible = "socionext,uniphier-ehci", "generic-ehci";
340 reg = <0x5a820100 0x100>;
341 interrupts = <0 82 4>;
342 clocks = <&mio 5>, <&mio 6>;
346 compatible = "socionext,uniphier-ehci", "generic-ehci";
348 reg = <0x5a830100 0x100>;
349 interrupts = <0 83 4>;
350 clocks = <&mio 7>, <&mio 6>;
354 compatible = "simple-mfd", "syscon";
355 reg = <0xf1830000 0x200>;
358 sysctrl: sysctrl@f1840000 {
359 compatible = "socionext,ph1-sld3-sysctrl";
360 reg = <0xf1840000 0x4000>;
366 nand: nand@f8000000 {
367 compatible = "denali,denali-nand-dt";
368 reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
369 reg-names = "nand_data", "denali_reg";