git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-ph1-sld3.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-sLD3 SoC
   3  *
   4  * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         compatible = "socionext,ph1-sld3";
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17                 enable-method = "socionext,uniphier-smp";
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                 };
  24
  25                 cpu@1 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         reg = <1>;
  29                 };
  30         };
  31
  32         clocks {
  33                 refclk: ref {
  34                         #clock-cells = <0>;
  35                         compatible = "fixed-clock";
  36                         clock-frequency = <24576000>;
  37                 };
  38
  39                 arm_timer_clk: arm_timer_clk {
  40                         #clock-cells = <0>;
  41                         compatible = "fixed-clock";
  42                         clock-frequency = <50000000>;
  43                 };
  44
  45                 uart_clk: uart_clk {
  46                         #clock-cells = <0>;
  47                         compatible = "fixed-clock";
  48                         clock-frequency = <36864000>;
  49                 };
  50
  51                 iobus_clk: iobus_clk {
  52                         #clock-cells = <0>;
  53                         compatible = "fixed-clock";
  54                         clock-frequency = <100000000>;
  55                 };
  56         };
  57
  58         soc {
  59                 compatible = "simple-bus";
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 ranges;
  63                 interrupt-parent = <&intc>;
  64
  65                 extbus: extbus {
  66                         compatible = "simple-bus";
  67                         #address-cells = <2>;
  68                         #size-cells = <1>;
  69                 };
  70
  71                 timer@20000200 {
  72                         compatible = "arm,cortex-a9-global-timer";
  73                         reg = <0x20000200 0x20>;
  74                         interrupts = <1 11 0x304>;
  75                         clocks = <&arm_timer_clk>;
  76                 };
  77
  78                 timer@20000600 {
  79                         compatible = "arm,cortex-a9-twd-timer";
  80                         reg = <0x20000600 0x20>;
  81                         interrupts = <1 13 0x304>;
  82                         clocks = <&arm_timer_clk>;
  83                 };
  84
  85                 intc: interrupt-controller@20001000 {
  86                         compatible = "arm,cortex-a9-gic";
  87                         #interrupt-cells = <3>;
  88                         interrupt-controller;
  89                         reg = <0x20001000 0x1000>,
  90                               <0x20000100 0x100>;
  91                 };
  92
  93                 serial0: serial@54006800 {
  94                         compatible = "socionext,uniphier-uart";
  95                         status = "disabled";
  96                         reg = <0x54006800 0x40>;
  97                         interrupts = <0 33 4>;
  98                         clocks = <&uart_clk>;
  99                         clock-frequency = <36864000>;
 100                 };
 101
 102                 serial1: serial@54006900 {
 103                         compatible = "socionext,uniphier-uart";
 104                         status = "disabled";
 105                         reg = <0x54006900 0x40>;
 106                         interrupts = <0 35 4>;
 107                         clocks = <&uart_clk>;
 108                         clock-frequency = <36864000>;
 109                 };
 110
 111                 serial2: serial@54006a00 {
 112                         compatible = "socionext,uniphier-uart";
 113                         status = "disabled";
 114                         reg = <0x54006a00 0x40>;
 115                         interrupts = <0 37 4>;
 116                         clocks = <&uart_clk>;
 117                         clock-frequency = <36864000>;
 118                 };
 119
 120                 i2c0: i2c@58400000 {
 121                         compatible = "socionext,uniphier-i2c";
 122                         status = "disabled";
 123                         reg = <0x58400000 0x40>;
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                         interrupts = <0 41 1>;
 127                         clocks = <&iobus_clk>;
 128                         clock-frequency = <100000>;
 129                 };
 130
 131                 i2c1: i2c@58480000 {
 132                         compatible = "socionext,uniphier-i2c";
 133                         status = "disabled";
 134                         reg = <0x58480000 0x40>;
 135                         #address-cells = <1>;
 136                         #size-cells = <0>;
 137                         interrupts = <0 42 1>;
 138                         clocks = <&iobus_clk>;
 139                         clock-frequency = <100000>;
 140                 };
 141
 142                 i2c2: i2c@58500000 {
 143                         compatible = "socionext,uniphier-i2c";
 144                         status = "disabled";
 145                         reg = <0x58500000 0x40>;
 146                         #address-cells = <1>;
 147                         #size-cells = <0>;
 148                         interrupts = <0 43 1>;
 149                         clocks = <&iobus_clk>;
 150                         clock-frequency = <100000>;
 151                 };
 152
 153                 i2c3: i2c@58580000 {
 154                         compatible = "socionext,uniphier-i2c";
 155                         status = "disabled";
 156                         reg = <0x58580000 0x40>;
 157                         #address-cells = <1>;
 158                         #size-cells = <0>;
 159                         interrupts = <0 44 1>;
 160                         clocks = <&iobus_clk>;
 161                         clock-frequency = <100000>;
 162                 };
 163
 164                 /* chip-internal connection for DMD */
 165                 i2c4: i2c@58600000 {
 166                         compatible = "socionext,uniphier-i2c";
 167                         reg = <0x58600000 0x40>;
 168                         #address-cells = <1>;
 169                         #size-cells = <0>;
 170                         interrupts = <0 45 1>;
 171                         clocks = <&iobus_clk>;
 172                         clock-frequency = <400000>;
 173                 };
 174
 175                 system-bus-controller-misc@59800000 {
 176                         compatible = "socionext,uniphier-system-bus-controller-misc",
 177                                      "syscon";
 178                         reg = <0x59800000 0x2000>;
 179                 };
 180
 181                 mio: mioctrl@59810000 {
 182                         compatible = "socionext,ph1-sld3-mioctrl";
 183                         reg = <0x59810000 0x800>;
 184                         #clock-cells = <1>;
 185                         clock-names = "stdmac", "ehci";
 186                         clocks = <&sysctrl 10>, <&sysctrl 18>;
 187                 };
 188
 189                 usb0: usb@5a800100 {
 190                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 191                         status = "disabled";
 192                         reg = <0x5a800100 0x100>;
 193                         interrupts = <0 80 4>;
 194                         clocks = <&mio 3>, <&mio 6>;
 195                 };
 196
 197                 usb1: usb@5a810100 {
 198                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 199                         status = "disabled";
 200                         reg = <0x5a810100 0x100>;
 201                         interrupts = <0 81 4>;
 202                         clocks = <&mio 4>, <&mio 6>;
 203                 };
 204
 205                 usb2: usb@5a820100 {
 206                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 207                         status = "disabled";
 208                         reg = <0x5a820100 0x100>;
 209                         interrupts = <0 82 4>;
 210                         clocks = <&mio 5>, <&mio 6>;
 211                 };
 212
 213                 usb3: usb@5a830100 {
 214                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 215                         status = "disabled";
 216                         reg = <0x5a830100 0x100>;
 217                         interrupts = <0 83 4>;
 218                         clocks = <&mio 7>, <&mio 6>;
 219                 };
 220
 221                 sysctrl: sysctrl@f1840000 {
 222                         compatible = "socionext,ph1-sld3-sysctrl";
 223                         reg = <0xf1840000 0x4000>;
 224                         #clock-cells = <1>;
 225                         clock-names = "ref";
 226                         clocks = <&refclk>;
 227                 };
 228
 229                 nand: nand@f8000000 {
 230                         compatible = "denali,denali-nand-dt";
 231                         reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
 232                         reg-names = "nand_data", "denali_reg";
 233                 };
 234         };
 235 };