2 * Device Tree Source for UniPhier PH1-sLD3 SoC
4 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /include/ "skeleton.dtsi"
12 compatible = "socionext,ph1-sld3";
17 enable-method = "socionext,uniphier-smp";
21 compatible = "arm,cortex-a9";
27 compatible = "arm,cortex-a9";
35 compatible = "fixed-clock";
36 clock-frequency = <24576000>;
39 arm_timer_clk: arm_timer_clk {
41 compatible = "fixed-clock";
42 clock-frequency = <50000000>;
47 compatible = "fixed-clock";
48 clock-frequency = <36864000>;
51 iobus_clk: iobus_clk {
53 compatible = "fixed-clock";
54 clock-frequency = <100000000>;
59 compatible = "simple-bus";
63 interrupt-parent = <&intc>;
66 compatible = "simple-bus";
72 compatible = "arm,cortex-a9-global-timer";
73 reg = <0x20000200 0x20>;
74 interrupts = <1 11 0x304>;
75 clocks = <&arm_timer_clk>;
79 compatible = "arm,cortex-a9-twd-timer";
80 reg = <0x20000600 0x20>;
81 interrupts = <1 13 0x304>;
82 clocks = <&arm_timer_clk>;
85 intc: interrupt-controller@20001000 {
86 compatible = "arm,cortex-a9-gic";
87 #interrupt-cells = <3>;
89 reg = <0x20001000 0x1000>,
93 serial0: serial@54006800 {
94 compatible = "socionext,uniphier-uart";
96 reg = <0x54006800 0x40>;
97 interrupts = <0 33 4>;
99 clock-frequency = <36864000>;
102 serial1: serial@54006900 {
103 compatible = "socionext,uniphier-uart";
105 reg = <0x54006900 0x40>;
106 interrupts = <0 35 4>;
107 clocks = <&uart_clk>;
108 clock-frequency = <36864000>;
111 serial2: serial@54006a00 {
112 compatible = "socionext,uniphier-uart";
114 reg = <0x54006a00 0x40>;
115 interrupts = <0 37 4>;
116 clocks = <&uart_clk>;
117 clock-frequency = <36864000>;
121 compatible = "socionext,uniphier-i2c";
123 reg = <0x58400000 0x40>;
124 #address-cells = <1>;
126 interrupts = <0 41 1>;
127 clocks = <&iobus_clk>;
128 clock-frequency = <100000>;
132 compatible = "socionext,uniphier-i2c";
134 reg = <0x58480000 0x40>;
135 #address-cells = <1>;
137 interrupts = <0 42 1>;
138 clocks = <&iobus_clk>;
139 clock-frequency = <100000>;
143 compatible = "socionext,uniphier-i2c";
145 reg = <0x58500000 0x40>;
146 #address-cells = <1>;
148 interrupts = <0 43 1>;
149 clocks = <&iobus_clk>;
150 clock-frequency = <100000>;
154 compatible = "socionext,uniphier-i2c";
156 reg = <0x58580000 0x40>;
157 #address-cells = <1>;
159 interrupts = <0 44 1>;
160 clocks = <&iobus_clk>;
161 clock-frequency = <100000>;
164 /* chip-internal connection for DMD */
166 compatible = "socionext,uniphier-i2c";
167 reg = <0x58600000 0x40>;
168 #address-cells = <1>;
170 interrupts = <0 45 1>;
171 clocks = <&iobus_clk>;
172 clock-frequency = <400000>;
175 system-bus-controller-misc@59800000 {
176 compatible = "socionext,uniphier-system-bus-controller-misc",
178 reg = <0x59800000 0x2000>;
181 mio: mioctrl@59810000 {
182 compatible = "socionext,ph1-sld3-mioctrl";
183 reg = <0x59810000 0x800>;
185 clock-names = "stdmac", "ehci";
186 clocks = <&sysctrl 10>, <&sysctrl 18>;
190 compatible = "socionext,uniphier-ehci", "generic-ehci";
192 reg = <0x5a800100 0x100>;
193 interrupts = <0 80 4>;
194 clocks = <&mio 3>, <&mio 6>;
198 compatible = "socionext,uniphier-ehci", "generic-ehci";
200 reg = <0x5a810100 0x100>;
201 interrupts = <0 81 4>;
202 clocks = <&mio 4>, <&mio 6>;
206 compatible = "socionext,uniphier-ehci", "generic-ehci";
208 reg = <0x5a820100 0x100>;
209 interrupts = <0 82 4>;
210 clocks = <&mio 5>, <&mio 6>;
214 compatible = "socionext,uniphier-ehci", "generic-ehci";
216 reg = <0x5a830100 0x100>;
217 interrupts = <0 83 4>;
218 clocks = <&mio 7>, <&mio 6>;
221 sysctrl: sysctrl@f1840000 {
222 compatible = "socionext,ph1-sld3-sysctrl";
223 reg = <0xf1840000 0x4000>;
229 nand: nand@f8000000 {
230 compatible = "denali,denali-nand-dt";
231 reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
232 reg-names = "nand_data", "denali_reg";