git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-ph1-sld3.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-sLD3 SoC
   3  *
   4  * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         compatible = "socionext,ph1-sld3";
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17                 enable-method = "socionext,uniphier-smp";
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                 };
  24
  25                 cpu@1 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         reg = <1>;
  29                 };
  30         };
  31
  32         clocks {
  33                 refclk: ref {
  34                         #clock-cells = <0>;
  35                         compatible = "fixed-clock";
  36                         clock-frequency = <24576000>;
  37                 };
  38
  39                 arm_timer_clk: arm_timer_clk {
  40                         #clock-cells = <0>;
  41                         compatible = "fixed-clock";
  42                         clock-frequency = <50000000>;
  43                 };
  44
  45                 iobus_clk: iobus_clk {
  46                         #clock-cells = <0>;
  47                         compatible = "fixed-clock";
  48                         clock-frequency = <100000000>;
  49                 };
  50         };
  51
  52         soc {
  53                 compatible = "simple-bus";
  54                 #address-cells = <1>;
  55                 #size-cells = <1>;
  56                 ranges;
  57                 interrupt-parent = <&intc>;
  58                 u-boot,dm-pre-reloc;
  59
  60                 timer@20000200 {
  61                         compatible = "arm,cortex-a9-global-timer";
  62                         reg = <0x20000200 0x20>;
  63                         interrupts = <1 11 0x304>;
  64                         clocks = <&arm_timer_clk>;
  65                 };
  66
  67                 timer@20000600 {
  68                         compatible = "arm,cortex-a9-twd-timer";
  69                         reg = <0x20000600 0x20>;
  70                         interrupts = <1 13 0x304>;
  71                         clocks = <&arm_timer_clk>;
  72                 };
  73
  74                 intc: interrupt-controller@20001000 {
  75                         compatible = "arm,cortex-a9-gic";
  76                         #interrupt-cells = <3>;
  77                         interrupt-controller;
  78                         reg = <0x20001000 0x1000>,
  79                               <0x20000100 0x100>;
  80                 };
  81
  82                 serial0: serial@54006800 {
  83                         compatible = "socionext,uniphier-uart";
  84                         status = "disabled";
  85                         reg = <0x54006800 0x40>;
  86                         interrupts = <0 33 4>;
  87                         pinctrl-names = "default";
  88                         pinctrl-0 = <&pinctrl_uart0>;
  89                         clock-frequency = <36864000>;
  90                 };
  91
  92                 serial1: serial@54006900 {
  93                         compatible = "socionext,uniphier-uart";
  94                         status = "disabled";
  95                         reg = <0x54006900 0x40>;
  96                         interrupts = <0 35 4>;
  97                         pinctrl-names = "default";
  98                         pinctrl-0 = <&pinctrl_uart1>;
  99                         clock-frequency = <36864000>;
 100                 };
 101
 102                 serial2: serial@54006a00 {
 103                         compatible = "socionext,uniphier-uart";
 104                         status = "disabled";
 105                         reg = <0x54006a00 0x40>;
 106                         interrupts = <0 37 4>;
 107                         pinctrl-names = "default";
 108                         pinctrl-0 = <&pinctrl_uart2>;
 109                         clock-frequency = <36864000>;
 110                 };
 111
 112                 port0x: gpio@55000008 {
 113                         compatible = "socionext,uniphier-gpio";
 114                         reg = <0x55000008 0x8>;
 115                         gpio-controller;
 116                         #gpio-cells = <2>;
 117                 };
 118
 119                 port1x: gpio@55000010 {
 120                         compatible = "socionext,uniphier-gpio";
 121                         reg = <0x55000010 0x8>;
 122                         gpio-controller;
 123                         #gpio-cells = <2>;
 124                 };
 125
 126                 port2x: gpio@55000018 {
 127                         compatible = "socionext,uniphier-gpio";
 128                         reg = <0x55000018 0x8>;
 129                         gpio-controller;
 130                         #gpio-cells = <2>;
 131                 };
 132
 133                 port3x: gpio@55000020 {
 134                         compatible = "socionext,uniphier-gpio";
 135                         reg = <0x55000020 0x8>;
 136                         gpio-controller;
 137                         #gpio-cells = <2>;
 138                 };
 139
 140                 port4: gpio@55000028 {
 141                         compatible = "socionext,uniphier-gpio";
 142                         reg = <0x55000028 0x8>;
 143                         gpio-controller;
 144                         #gpio-cells = <2>;
 145                 };
 146
 147                 port5x: gpio@55000030 {
 148                         compatible = "socionext,uniphier-gpio";
 149                         reg = <0x55000030 0x8>;
 150                         gpio-controller;
 151                         #gpio-cells = <2>;
 152                 };
 153
 154                 port6x: gpio@55000038 {
 155                         compatible = "socionext,uniphier-gpio";
 156                         reg = <0x55000038 0x8>;
 157                         gpio-controller;
 158                         #gpio-cells = <2>;
 159                 };
 160
 161                 port7x: gpio@55000040 {
 162                         compatible = "socionext,uniphier-gpio";
 163                         reg = <0x55000040 0x8>;
 164                         gpio-controller;
 165                         #gpio-cells = <2>;
 166                 };
 167
 168                 port8x: gpio@55000048 {
 169                         compatible = "socionext,uniphier-gpio";
 170                         reg = <0x55000048 0x8>;
 171                         gpio-controller;
 172                         #gpio-cells = <2>;
 173                 };
 174
 175                 port9x: gpio@55000050 {
 176                         compatible = "socionext,uniphier-gpio";
 177                         reg = <0x55000050 0x8>;
 178                         gpio-controller;
 179                         #gpio-cells = <2>;
 180                 };
 181
 182                 port10x: gpio@55000058 {
 183                         compatible = "socionext,uniphier-gpio";
 184                         reg = <0x55000058 0x8>;
 185                         gpio-controller;
 186                         #gpio-cells = <2>;
 187                 };
 188
 189                 port11x: gpio@55000060 {
 190                         compatible = "socionext,uniphier-gpio";
 191                         reg = <0x55000060 0x8>;
 192                         gpio-controller;
 193                         #gpio-cells = <2>;
 194                 };
 195
 196                 port12x: gpio@55000068 {
 197                         compatible = "socionext,uniphier-gpio";
 198                         reg = <0x55000068 0x8>;
 199                         gpio-controller;
 200                         #gpio-cells = <2>;
 201                 };
 202
 203                 port13x: gpio@55000070 {
 204                         compatible = "socionext,uniphier-gpio";
 205                         reg = <0x55000070 0x8>;
 206                         gpio-controller;
 207                         #gpio-cells = <2>;
 208                 };
 209
 210                 port14x: gpio@55000078 {
 211                         compatible = "socionext,uniphier-gpio";
 212                         reg = <0x55000078 0x8>;
 213                         gpio-controller;
 214                         #gpio-cells = <2>;
 215                 };
 216
 217                 port16x: gpio@55000088 {
 218                         compatible = "socionext,uniphier-gpio";
 219                         reg = <0x55000088 0x8>;
 220                         gpio-controller;
 221                         #gpio-cells = <2>;
 222                 };
 223
 224                 i2c0: i2c@58400000 {
 225                         compatible = "socionext,uniphier-i2c";
 226                         status = "disabled";
 227                         reg = <0x58400000 0x40>;
 228                         #address-cells = <1>;
 229                         #size-cells = <0>;
 230                         interrupts = <0 41 1>;
 231                         pinctrl-names = "default";
 232                         pinctrl-0 = <&pinctrl_i2c0>;
 233                         clocks = <&iobus_clk>;
 234                         clock-frequency = <100000>;
 235                 };
 236
 237                 i2c1: i2c@58480000 {
 238                         compatible = "socionext,uniphier-i2c";
 239                         status = "disabled";
 240                         reg = <0x58480000 0x40>;
 241                         #address-cells = <1>;
 242                         #size-cells = <0>;
 243                         interrupts = <0 42 1>;
 244                         clocks = <&iobus_clk>;
 245                         clock-frequency = <100000>;
 246                 };
 247
 248                 i2c2: i2c@58500000 {
 249                         compatible = "socionext,uniphier-i2c";
 250                         status = "disabled";
 251                         reg = <0x58500000 0x40>;
 252                         #address-cells = <1>;
 253                         #size-cells = <0>;
 254                         interrupts = <0 43 1>;
 255                         clocks = <&iobus_clk>;
 256                         clock-frequency = <100000>;
 257                 };
 258
 259                 i2c3: i2c@58580000 {
 260                         compatible = "socionext,uniphier-i2c";
 261                         status = "disabled";
 262                         reg = <0x58580000 0x40>;
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                         interrupts = <0 44 1>;
 266                         clocks = <&iobus_clk>;
 267                         clock-frequency = <100000>;
 268                 };
 269
 270                 /* chip-internal connection for DMD */
 271                 i2c4: i2c@58600000 {
 272                         compatible = "socionext,uniphier-i2c";
 273                         reg = <0x58600000 0x40>;
 274                         #address-cells = <1>;
 275                         #size-cells = <0>;
 276                         interrupts = <0 45 1>;
 277                         clocks = <&iobus_clk>;
 278                         clock-frequency = <400000>;
 279                 };
 280
 281                 system_bus: system-bus@58c00000 {
 282                         compatible = "socionext,uniphier-system-bus";
 283                         reg = <0x58c00000 0x400>;
 284                         #address-cells = <2>;
 285                         #size-cells = <1>;
 286                 };
 287
 288                 smpctrl@59800000 {
 289                         compatible = "socionext,uniphier-smpctrl";
 290                         reg = <0x59801000 0x400>;
 291                 };
 292
 293                 mioctrl@59810000 {
 294                         compatible = "socionext,uniphier-mioctrl",
 295                                      "simple-mfd", "syscon";
 296                         reg = <0x59810000 0x800>;
 297                         u-boot,dm-pre-reloc;
 298
 299                         mio_clk: clock {
 300                                 compatible = "socionext,uniphier-sld3-mio-clock";
 301                                 #clock-cells = <1>;
 302                                 u-boot,dm-pre-reloc;
 303                         };
 304
 305                         mio_rst: reset {
 306                                 compatible = "socionext,uniphier-sld3-mio-reset";
 307                                 #reset-cells = <1>;
 308                         };
 309                 };
 310
 311                 emmc: sdhc@5a400000 {
 312                         compatible = "socionext,uniphier-sdhc";
 313                         status = "disabled";
 314                         reg = <0x5a400000 0x200>;
 315                         interrupts = <0 78 4>;
 316                         pinctrl-names = "default", "1.8v";
 317                         pinctrl-0 = <&pinctrl_emmc>;
 318                         pinctrl-1 = <&pinctrl_emmc_1v8>;
 319                         clocks = <&mio_clk 1>;
 320                         bus-width = <8>;
 321                         non-removable;
 322                 };
 323
 324                 sd: sdhc@5a500000 {
 325                         compatible = "socionext,uniphier-sdhc";
 326                         status = "disabled";
 327                         reg = <0x5a500000 0x200>;
 328                         interrupts = <0 76 4>;
 329                         pinctrl-names = "default", "1.8v";
 330                         pinctrl-0 = <&pinctrl_sd>;
 331                         pinctrl-1 = <&pinctrl_sd_1v8>;
 332                         clocks = <&mio_clk 0>;
 333                         bus-width = <4>;
 334                 };
 335
 336                 usb0: usb@5a800100 {
 337                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 338                         status = "disabled";
 339                         reg = <0x5a800100 0x100>;
 340                         interrupts = <0 80 4>;
 341                         pinctrl-names = "default";
 342                         pinctrl-0 = <&pinctrl_usb0>;
 343                         clocks = <&mio_clk 3>, <&mio_clk 6>;
 344                 };
 345
 346                 usb1: usb@5a810100 {
 347                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 348                         status = "disabled";
 349                         reg = <0x5a810100 0x100>;
 350                         interrupts = <0 81 4>;
 351                         pinctrl-names = "default";
 352                         pinctrl-0 = <&pinctrl_usb1>;
 353                         clocks = <&mio_clk 4>, <&mio_clk 6>;
 354                 };
 355
 356                 usb2: usb@5a820100 {
 357                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 358                         status = "disabled";
 359                         reg = <0x5a820100 0x100>;
 360                         interrupts = <0 82 4>;
 361                         pinctrl-names = "default";
 362                         pinctrl-0 = <&pinctrl_usb2>;
 363                         clocks = <&mio_clk 5>, <&mio_clk 6>;
 364                 };
 365
 366                 usb3: usb@5a830100 {
 367                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 368                         status = "disabled";
 369                         reg = <0x5a830100 0x100>;
 370                         interrupts = <0 83 4>;
 371                         pinctrl-names = "default";
 372                         pinctrl-0 = <&pinctrl_usb3>;
 373                         clocks = <&mio_clk 7>, <&mio_clk 6>;
 374                 };
 375
 376                 soc-glue@5f800000 {
 377                         compatible = "simple-mfd", "syscon";
 378                         reg = <0x5f800000 0x2000>;
 379                         u-boot,dm-pre-reloc;
 380
 381                         pinctrl: pinctrl {
 382                                 compatible = "socionext,uniphier-sld3-pinctrl";
 383                                 u-boot,dm-pre-reloc;
 384                         };
 385                 };
 386
 387                 aidet@f1830000 {
 388                         compatible = "simple-mfd", "syscon";
 389                         reg = <0xf1830000 0x200>;
 390                 };
 391
 392                 sysctrl@f1840000 {
 393                         compatible = "socionext,uniphier-sysctrl",
 394                                      "simple-mfd", "syscon";
 395                         reg = <0xf1840000 0x4000>;
 396
 397                         sys_clk: clock {
 398                                 compatible = "socionext,uniphier-sld3-clock";
 399                                 #clock-cells = <1>;
 400                         };
 401
 402                         sys_rst: reset {
 403                                 compatible = "socionext,uniphier-sld3-reset";
 404                                 #reset-cells = <1>;
 405                         };
 406                 };
 407
 408                 nand: nand@f8000000 {
 409                         compatible = "denali,denali-nand-dt";
 410                         reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
 411                         reg-names = "nand_data", "denali_reg";
 412                 };
 413         };
 414 };
 415
 416 /include/ "uniphier-pinctrl.dtsi"