2 * Device Tree Source for UniPhier PH1-sLD3 SoC
4 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /include/ "skeleton.dtsi"
12 compatible = "socionext,ph1-sld3";
17 enable-method = "socionext,uniphier-smp";
21 compatible = "arm,cortex-a9";
27 compatible = "arm,cortex-a9";
35 compatible = "fixed-clock";
36 clock-frequency = <24576000>;
39 arm_timer_clk: arm_timer_clk {
41 compatible = "fixed-clock";
42 clock-frequency = <50000000>;
45 iobus_clk: iobus_clk {
47 compatible = "fixed-clock";
48 clock-frequency = <100000000>;
53 compatible = "simple-bus";
57 interrupt-parent = <&intc>;
61 compatible = "arm,cortex-a9-global-timer";
62 reg = <0x20000200 0x20>;
63 interrupts = <1 11 0x304>;
64 clocks = <&arm_timer_clk>;
68 compatible = "arm,cortex-a9-twd-timer";
69 reg = <0x20000600 0x20>;
70 interrupts = <1 13 0x304>;
71 clocks = <&arm_timer_clk>;
74 intc: interrupt-controller@20001000 {
75 compatible = "arm,cortex-a9-gic";
76 #interrupt-cells = <3>;
78 reg = <0x20001000 0x1000>,
82 serial0: serial@54006800 {
83 compatible = "socionext,uniphier-uart";
85 reg = <0x54006800 0x40>;
86 interrupts = <0 33 4>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_uart0>;
89 clock-frequency = <36864000>;
92 serial1: serial@54006900 {
93 compatible = "socionext,uniphier-uart";
95 reg = <0x54006900 0x40>;
96 interrupts = <0 35 4>;
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_uart1>;
99 clock-frequency = <36864000>;
102 serial2: serial@54006a00 {
103 compatible = "socionext,uniphier-uart";
105 reg = <0x54006a00 0x40>;
106 interrupts = <0 37 4>;
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_uart2>;
109 clock-frequency = <36864000>;
112 port0x: gpio@55000008 {
113 compatible = "socionext,uniphier-gpio";
114 reg = <0x55000008 0x8>;
119 port1x: gpio@55000010 {
120 compatible = "socionext,uniphier-gpio";
121 reg = <0x55000010 0x8>;
126 port2x: gpio@55000018 {
127 compatible = "socionext,uniphier-gpio";
128 reg = <0x55000018 0x8>;
133 port3x: gpio@55000020 {
134 compatible = "socionext,uniphier-gpio";
135 reg = <0x55000020 0x8>;
140 port4: gpio@55000028 {
141 compatible = "socionext,uniphier-gpio";
142 reg = <0x55000028 0x8>;
147 port5x: gpio@55000030 {
148 compatible = "socionext,uniphier-gpio";
149 reg = <0x55000030 0x8>;
154 port6x: gpio@55000038 {
155 compatible = "socionext,uniphier-gpio";
156 reg = <0x55000038 0x8>;
161 port7x: gpio@55000040 {
162 compatible = "socionext,uniphier-gpio";
163 reg = <0x55000040 0x8>;
168 port8x: gpio@55000048 {
169 compatible = "socionext,uniphier-gpio";
170 reg = <0x55000048 0x8>;
175 port9x: gpio@55000050 {
176 compatible = "socionext,uniphier-gpio";
177 reg = <0x55000050 0x8>;
182 port10x: gpio@55000058 {
183 compatible = "socionext,uniphier-gpio";
184 reg = <0x55000058 0x8>;
189 port11x: gpio@55000060 {
190 compatible = "socionext,uniphier-gpio";
191 reg = <0x55000060 0x8>;
196 port12x: gpio@55000068 {
197 compatible = "socionext,uniphier-gpio";
198 reg = <0x55000068 0x8>;
203 port13x: gpio@55000070 {
204 compatible = "socionext,uniphier-gpio";
205 reg = <0x55000070 0x8>;
210 port14x: gpio@55000078 {
211 compatible = "socionext,uniphier-gpio";
212 reg = <0x55000078 0x8>;
217 port16x: gpio@55000088 {
218 compatible = "socionext,uniphier-gpio";
219 reg = <0x55000088 0x8>;
225 compatible = "socionext,uniphier-i2c";
227 reg = <0x58400000 0x40>;
228 #address-cells = <1>;
230 interrupts = <0 41 1>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_i2c0>;
233 clocks = <&iobus_clk>;
234 clock-frequency = <100000>;
238 compatible = "socionext,uniphier-i2c";
240 reg = <0x58480000 0x40>;
241 #address-cells = <1>;
243 interrupts = <0 42 1>;
244 clocks = <&iobus_clk>;
245 clock-frequency = <100000>;
249 compatible = "socionext,uniphier-i2c";
251 reg = <0x58500000 0x40>;
252 #address-cells = <1>;
254 interrupts = <0 43 1>;
255 clocks = <&iobus_clk>;
256 clock-frequency = <100000>;
260 compatible = "socionext,uniphier-i2c";
262 reg = <0x58580000 0x40>;
263 #address-cells = <1>;
265 interrupts = <0 44 1>;
266 clocks = <&iobus_clk>;
267 clock-frequency = <100000>;
270 /* chip-internal connection for DMD */
272 compatible = "socionext,uniphier-i2c";
273 reg = <0x58600000 0x40>;
274 #address-cells = <1>;
276 interrupts = <0 45 1>;
277 clocks = <&iobus_clk>;
278 clock-frequency = <400000>;
281 system_bus: system-bus@58c00000 {
282 compatible = "socionext,uniphier-system-bus";
283 reg = <0x58c00000 0x400>;
284 #address-cells = <2>;
289 compatible = "socionext,uniphier-smpctrl";
290 reg = <0x59801000 0x400>;
294 compatible = "socionext,uniphier-mioctrl",
295 "simple-mfd", "syscon";
296 reg = <0x59810000 0x800>;
300 compatible = "socionext,uniphier-sld3-mio-clock";
306 compatible = "socionext,uniphier-sld3-mio-reset";
311 emmc: sdhc@5a400000 {
312 compatible = "socionext,uniphier-sdhc";
314 reg = <0x5a400000 0x200>;
315 interrupts = <0 78 4>;
316 pinctrl-names = "default", "1.8v";
317 pinctrl-0 = <&pinctrl_emmc>;
318 pinctrl-1 = <&pinctrl_emmc_1v8>;
319 clocks = <&mio_clk 1>;
325 compatible = "socionext,uniphier-sdhc";
327 reg = <0x5a500000 0x200>;
328 interrupts = <0 76 4>;
329 pinctrl-names = "default", "1.8v";
330 pinctrl-0 = <&pinctrl_sd>;
331 pinctrl-1 = <&pinctrl_sd_1v8>;
332 clocks = <&mio_clk 0>;
337 compatible = "socionext,uniphier-ehci", "generic-ehci";
339 reg = <0x5a800100 0x100>;
340 interrupts = <0 80 4>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_usb0>;
343 clocks = <&mio_clk 3>, <&mio_clk 6>;
347 compatible = "socionext,uniphier-ehci", "generic-ehci";
349 reg = <0x5a810100 0x100>;
350 interrupts = <0 81 4>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_usb1>;
353 clocks = <&mio_clk 4>, <&mio_clk 6>;
357 compatible = "socionext,uniphier-ehci", "generic-ehci";
359 reg = <0x5a820100 0x100>;
360 interrupts = <0 82 4>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_usb2>;
363 clocks = <&mio_clk 5>, <&mio_clk 6>;
367 compatible = "socionext,uniphier-ehci", "generic-ehci";
369 reg = <0x5a830100 0x100>;
370 interrupts = <0 83 4>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_usb3>;
373 clocks = <&mio_clk 7>, <&mio_clk 6>;
377 compatible = "simple-mfd", "syscon";
378 reg = <0x5f800000 0x2000>;
382 compatible = "socionext,uniphier-sld3-pinctrl";
388 compatible = "simple-mfd", "syscon";
389 reg = <0xf1830000 0x200>;
393 compatible = "socionext,uniphier-sysctrl",
394 "simple-mfd", "syscon";
395 reg = <0xf1840000 0x4000>;
398 compatible = "socionext,uniphier-sld3-clock";
403 compatible = "socionext,uniphier-sld3-reset";
408 nand: nand@f8000000 {
409 compatible = "denali,denali-nand-dt";
410 reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
411 reg-names = "nand_data", "denali_reg";
416 /include/ "uniphier-pinctrl.dtsi"