git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-ph1-sld3.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-sLD3 SoC
   3  *
   4  * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+        X11
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         compatible = "socionext,ph1-sld3";
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17                 enable-method = "socionext,uniphier-smp";
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                 };
  24
  25                 cpu@1 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         reg = <1>;
  29                 };
  30         };
  31
  32         clocks {
  33                 refclk: ref {
  34                         #clock-cells = <0>;
  35                         compatible = "fixed-clock";
  36                         clock-frequency = <24576000>;
  37                 };
  38
  39                 arm_timer_clk: arm_timer_clk {
  40                         #clock-cells = <0>;
  41                         compatible = "fixed-clock";
  42                         clock-frequency = <50000000>;
  43                 };
  44
  45                 uart_clk: uart_clk {
  46                         #clock-cells = <0>;
  47                         compatible = "fixed-clock";
  48                         clock-frequency = <36864000>;
  49                 };
  50
  51                 iobus_clk: iobus_clk {
  52                         #clock-cells = <0>;
  53                         compatible = "fixed-clock";
  54                         clock-frequency = <100000000>;
  55                 };
  56         };
  57
  58         soc {
  59                 compatible = "simple-bus";
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 ranges;
  63                 interrupt-parent = <&intc>;
  64                 u-boot,dm-pre-reloc;
  65
  66                 timer@20000200 {
  67                         compatible = "arm,cortex-a9-global-timer";
  68                         reg = <0x20000200 0x20>;
  69                         interrupts = <1 11 0x304>;
  70                         clocks = <&arm_timer_clk>;
  71                 };
  72
  73                 timer@20000600 {
  74                         compatible = "arm,cortex-a9-twd-timer";
  75                         reg = <0x20000600 0x20>;
  76                         interrupts = <1 13 0x304>;
  77                         clocks = <&arm_timer_clk>;
  78                 };
  79
  80                 intc: interrupt-controller@20001000 {
  81                         compatible = "arm,cortex-a9-gic";
  82                         #interrupt-cells = <3>;
  83                         interrupt-controller;
  84                         reg = <0x20001000 0x1000>,
  85                               <0x20000100 0x100>;
  86                 };
  87
  88                 serial0: serial@54006800 {
  89                         compatible = "socionext,uniphier-uart";
  90                         status = "disabled";
  91                         reg = <0x54006800 0x40>;
  92                         interrupts = <0 33 4>;
  93                         pinctrl-names = "default";
  94                         pinctrl-0 = <&pinctrl_uart0>;
  95                         clocks = <&uart_clk>;
  96                         clock-frequency = <36864000>;
  97                 };
  98
  99                 serial1: serial@54006900 {
 100                         compatible = "socionext,uniphier-uart";
 101                         status = "disabled";
 102                         reg = <0x54006900 0x40>;
 103                         interrupts = <0 35 4>;
 104                         pinctrl-names = "default";
 105                         pinctrl-0 = <&pinctrl_uart1>;
 106                         clocks = <&uart_clk>;
 107                         clock-frequency = <36864000>;
 108                 };
 109
 110                 serial2: serial@54006a00 {
 111                         compatible = "socionext,uniphier-uart";
 112                         status = "disabled";
 113                         reg = <0x54006a00 0x40>;
 114                         interrupts = <0 37 4>;
 115                         pinctrl-names = "default";
 116                         pinctrl-0 = <&pinctrl_uart2>;
 117                         clocks = <&uart_clk>;
 118                         clock-frequency = <36864000>;
 119                 };
 120
 121                 port0x: gpio@55000008 {
 122                         compatible = "socionext,uniphier-gpio";
 123                         reg = <0x55000008 0x8>;
 124                         gpio-controller;
 125                         #gpio-cells = <2>;
 126                 };
 127
 128                 port1x: gpio@55000010 {
 129                         compatible = "socionext,uniphier-gpio";
 130                         reg = <0x55000010 0x8>;
 131                         gpio-controller;
 132                         #gpio-cells = <2>;
 133                 };
 134
 135                 port2x: gpio@55000018 {
 136                         compatible = "socionext,uniphier-gpio";
 137                         reg = <0x55000018 0x8>;
 138                         gpio-controller;
 139                         #gpio-cells = <2>;
 140                 };
 141
 142                 port3x: gpio@55000020 {
 143                         compatible = "socionext,uniphier-gpio";
 144                         reg = <0x55000020 0x8>;
 145                         gpio-controller;
 146                         #gpio-cells = <2>;
 147                 };
 148
 149                 port4: gpio@55000028 {
 150                         compatible = "socionext,uniphier-gpio";
 151                         reg = <0x55000028 0x8>;
 152                         gpio-controller;
 153                         #gpio-cells = <2>;
 154                 };
 155
 156                 port5x: gpio@55000030 {
 157                         compatible = "socionext,uniphier-gpio";
 158                         reg = <0x55000030 0x8>;
 159                         gpio-controller;
 160                         #gpio-cells = <2>;
 161                 };
 162
 163                 port6x: gpio@55000038 {
 164                         compatible = "socionext,uniphier-gpio";
 165                         reg = <0x55000038 0x8>;
 166                         gpio-controller;
 167                         #gpio-cells = <2>;
 168                 };
 169
 170                 port7x: gpio@55000040 {
 171                         compatible = "socionext,uniphier-gpio";
 172                         reg = <0x55000040 0x8>;
 173                         gpio-controller;
 174                         #gpio-cells = <2>;
 175                 };
 176
 177                 port8x: gpio@55000048 {
 178                         compatible = "socionext,uniphier-gpio";
 179                         reg = <0x55000048 0x8>;
 180                         gpio-controller;
 181                         #gpio-cells = <2>;
 182                 };
 183
 184                 port9x: gpio@55000050 {
 185                         compatible = "socionext,uniphier-gpio";
 186                         reg = <0x55000050 0x8>;
 187                         gpio-controller;
 188                         #gpio-cells = <2>;
 189                 };
 190
 191                 port10x: gpio@55000058 {
 192                         compatible = "socionext,uniphier-gpio";
 193                         reg = <0x55000058 0x8>;
 194                         gpio-controller;
 195                         #gpio-cells = <2>;
 196                 };
 197
 198                 port11x: gpio@55000060 {
 199                         compatible = "socionext,uniphier-gpio";
 200                         reg = <0x55000060 0x8>;
 201                         gpio-controller;
 202                         #gpio-cells = <2>;
 203                 };
 204
 205                 port12x: gpio@55000068 {
 206                         compatible = "socionext,uniphier-gpio";
 207                         reg = <0x55000068 0x8>;
 208                         gpio-controller;
 209                         #gpio-cells = <2>;
 210                 };
 211
 212                 port13x: gpio@55000070 {
 213                         compatible = "socionext,uniphier-gpio";
 214                         reg = <0x55000070 0x8>;
 215                         gpio-controller;
 216                         #gpio-cells = <2>;
 217                 };
 218
 219                 port14x: gpio@55000078 {
 220                         compatible = "socionext,uniphier-gpio";
 221                         reg = <0x55000078 0x8>;
 222                         gpio-controller;
 223                         #gpio-cells = <2>;
 224                 };
 225
 226                 port16x: gpio@55000088 {
 227                         compatible = "socionext,uniphier-gpio";
 228                         reg = <0x55000088 0x8>;
 229                         gpio-controller;
 230                         #gpio-cells = <2>;
 231                 };
 232
 233                 i2c0: i2c@58400000 {
 234                         compatible = "socionext,uniphier-i2c";
 235                         status = "disabled";
 236                         reg = <0x58400000 0x40>;
 237                         #address-cells = <1>;
 238                         #size-cells = <0>;
 239                         interrupts = <0 41 1>;
 240                         pinctrl-names = "default";
 241                         pinctrl-0 = <&pinctrl_i2c0>;
 242                         clocks = <&iobus_clk>;
 243                         clock-frequency = <100000>;
 244                 };
 245
 246                 i2c1: i2c@58480000 {
 247                         compatible = "socionext,uniphier-i2c";
 248                         status = "disabled";
 249                         reg = <0x58480000 0x40>;
 250                         #address-cells = <1>;
 251                         #size-cells = <0>;
 252                         interrupts = <0 42 1>;
 253                         clocks = <&iobus_clk>;
 254                         clock-frequency = <100000>;
 255                 };
 256
 257                 i2c2: i2c@58500000 {
 258                         compatible = "socionext,uniphier-i2c";
 259                         status = "disabled";
 260                         reg = <0x58500000 0x40>;
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263                         interrupts = <0 43 1>;
 264                         clocks = <&iobus_clk>;
 265                         clock-frequency = <100000>;
 266                 };
 267
 268                 i2c3: i2c@58580000 {
 269                         compatible = "socionext,uniphier-i2c";
 270                         status = "disabled";
 271                         reg = <0x58580000 0x40>;
 272                         #address-cells = <1>;
 273                         #size-cells = <0>;
 274                         interrupts = <0 44 1>;
 275                         clocks = <&iobus_clk>;
 276                         clock-frequency = <100000>;
 277                 };
 278
 279                 /* chip-internal connection for DMD */
 280                 i2c4: i2c@58600000 {
 281                         compatible = "socionext,uniphier-i2c";
 282                         reg = <0x58600000 0x40>;
 283                         #address-cells = <1>;
 284                         #size-cells = <0>;
 285                         interrupts = <0 45 1>;
 286                         clocks = <&iobus_clk>;
 287                         clock-frequency = <400000>;
 288                 };
 289
 290                 system_bus: system-bus@58c00000 {
 291                         compatible = "socionext,uniphier-system-bus";
 292                         reg = <0x58c00000 0x400>;
 293                         #address-cells = <2>;
 294                         #size-cells = <1>;
 295                 };
 296
 297                 smpctrl@59800000 {
 298                         compatible = "socionext,uniphier-smpctrl";
 299                         reg = <0x59801000 0x400>;
 300                 };
 301
 302                 mio: mioctrl@59810000 {
 303                         compatible = "socionext,ph1-sld3-mioctrl";
 304                         reg = <0x59810000 0x800>;
 305                         #clock-cells = <1>;
 306                         clock-names = "stdmac", "ehci";
 307                         clocks = <&sysctrl 10>, <&sysctrl 18>;
 308                 };
 309
 310                 emmc: sdhc@5a400000 {
 311                         compatible = "socionext,uniphier-sdhc";
 312                         status = "disabled";
 313                         reg = <0x5a400000 0x200>;
 314                         interrupts = <0 78 4>;
 315                         pinctrl-names = "default", "1.8v";
 316                         pinctrl-0 = <&pinctrl_emmc>;
 317                         pinctrl-1 = <&pinctrl_emmc_1v8>;
 318                         clocks = <&mio 1>;
 319                         bus-width = <8>;
 320                         non-removable;
 321                 };
 322
 323                 sd: sdhc@5a500000 {
 324                         compatible = "socionext,uniphier-sdhc";
 325                         status = "disabled";
 326                         reg = <0x5a500000 0x200>;
 327                         interrupts = <0 76 4>;
 328                         pinctrl-names = "default", "1.8v";
 329                         pinctrl-0 = <&pinctrl_sd>;
 330                         pinctrl-1 = <&pinctrl_sd_1v8>;
 331                         clocks = <&mio 0>;
 332                         bus-width = <4>;
 333                 };
 334
 335                 usb0: usb@5a800100 {
 336                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 337                         status = "disabled";
 338                         reg = <0x5a800100 0x100>;
 339                         interrupts = <0 80 4>;
 340                         pinctrl-names = "default";
 341                         pinctrl-0 = <&pinctrl_usb0>;
 342                         clocks = <&mio 3>, <&mio 6>;
 343                 };
 344
 345                 usb1: usb@5a810100 {
 346                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 347                         status = "disabled";
 348                         reg = <0x5a810100 0x100>;
 349                         interrupts = <0 81 4>;
 350                         pinctrl-names = "default";
 351                         pinctrl-0 = <&pinctrl_usb1>;
 352                         clocks = <&mio 4>, <&mio 6>;
 353                 };
 354
 355                 usb2: usb@5a820100 {
 356                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 357                         status = "disabled";
 358                         reg = <0x5a820100 0x100>;
 359                         interrupts = <0 82 4>;
 360                         pinctrl-names = "default";
 361                         pinctrl-0 = <&pinctrl_usb2>;
 362                         clocks = <&mio 5>, <&mio 6>;
 363                 };
 364
 365                 usb3: usb@5a830100 {
 366                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 367                         status = "disabled";
 368                         reg = <0x5a830100 0x100>;
 369                         interrupts = <0 83 4>;
 370                         pinctrl-names = "default";
 371                         pinctrl-0 = <&pinctrl_usb3>;
 372                         clocks = <&mio 7>, <&mio 6>;
 373                 };
 374
 375                 soc-glue@5f800000 {
 376                         compatible = "simple-mfd", "syscon";
 377                         reg = <0x5f800000 0x2000>;
 378                         u-boot,dm-pre-reloc;
 379
 380                         pinctrl: pinctrl {
 381                                 compatible = "socionext,uniphier-sld3-pinctrl";
 382                                 u-boot,dm-pre-reloc;
 383                         };
 384                 };
 385
 386                 aidet@f1830000 {
 387                         compatible = "simple-mfd", "syscon";
 388                         reg = <0xf1830000 0x200>;
 389                 };
 390
 391                 sysctrl: sysctrl@f1840000 {
 392                         compatible = "socionext,ph1-sld3-sysctrl";
 393                         reg = <0xf1840000 0x4000>;
 394                         #clock-cells = <1>;
 395                         clock-names = "ref";
 396                         clocks = <&refclk>;
 397                 };
 398
 399                 nand: nand@f8000000 {
 400                         compatible = "denali,denali-nand-dt";
 401                         reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
 402                         reg-names = "nand_data", "denali_reg";
 403                 };
 404         };
 405 };
 406
 407 /include/ "uniphier-pinctrl.dtsi"