2 * Device Tree Source for UniPhier PH1-sLD8 SoC
4 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /include/ "uniphier-common32.dtsi"
12 compatible = "socionext,ph1-sld8";
20 compatible = "arm,cortex-a9";
22 next-level-cache = <&l2>;
27 arm_timer_clk: arm_timer_clk {
29 compatible = "fixed-clock";
30 clock-frequency = <50000000>;
33 iobus_clk: iobus_clk {
35 compatible = "fixed-clock";
36 clock-frequency = <100000000>;
42 l2: l2-cache@500c0000 {
43 compatible = "socionext,uniphier-system-cache";
44 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
45 interrupts = <0 174 4>, <0 175 4>;
47 cache-size = <(256 * 1024)>;
49 cache-line-size = <128>;
53 port0x: gpio@55000008 {
54 compatible = "socionext,uniphier-gpio";
55 reg = <0x55000008 0x8>;
60 port1x: gpio@55000010 {
61 compatible = "socionext,uniphier-gpio";
62 reg = <0x55000010 0x8>;
67 port2x: gpio@55000018 {
68 compatible = "socionext,uniphier-gpio";
69 reg = <0x55000018 0x8>;
74 port3x: gpio@55000020 {
75 compatible = "socionext,uniphier-gpio";
76 reg = <0x55000020 0x8>;
81 port4: gpio@55000028 {
82 compatible = "socionext,uniphier-gpio";
83 reg = <0x55000028 0x8>;
88 port5x: gpio@55000030 {
89 compatible = "socionext,uniphier-gpio";
90 reg = <0x55000030 0x8>;
95 port6x: gpio@55000038 {
96 compatible = "socionext,uniphier-gpio";
97 reg = <0x55000038 0x8>;
102 port7x: gpio@55000040 {
103 compatible = "socionext,uniphier-gpio";
104 reg = <0x55000040 0x8>;
109 port8x: gpio@55000048 {
110 compatible = "socionext,uniphier-gpio";
111 reg = <0x55000048 0x8>;
116 port9x: gpio@55000050 {
117 compatible = "socionext,uniphier-gpio";
118 reg = <0x55000050 0x8>;
123 port10x: gpio@55000058 {
124 compatible = "socionext,uniphier-gpio";
125 reg = <0x55000058 0x8>;
130 port11x: gpio@55000060 {
131 compatible = "socionext,uniphier-gpio";
132 reg = <0x55000060 0x8>;
137 port12x: gpio@55000068 {
138 compatible = "socionext,uniphier-gpio";
139 reg = <0x55000068 0x8>;
144 port13x: gpio@55000070 {
145 compatible = "socionext,uniphier-gpio";
146 reg = <0x55000070 0x8>;
151 port14x: gpio@55000078 {
152 compatible = "socionext,uniphier-gpio";
153 reg = <0x55000078 0x8>;
158 port16x: gpio@55000088 {
159 compatible = "socionext,uniphier-gpio";
160 reg = <0x55000088 0x8>;
166 compatible = "socionext,uniphier-i2c";
168 reg = <0x58400000 0x40>;
169 #address-cells = <1>;
171 interrupts = <0 41 1>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_i2c0>;
174 clocks = <&iobus_clk>;
175 clock-frequency = <100000>;
179 compatible = "socionext,uniphier-i2c";
181 reg = <0x58480000 0x40>;
182 #address-cells = <1>;
184 interrupts = <0 42 1>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_i2c1>;
187 clocks = <&iobus_clk>;
188 clock-frequency = <100000>;
191 /* chip-internal connection for DMD */
193 compatible = "socionext,uniphier-i2c";
194 reg = <0x58500000 0x40>;
195 #address-cells = <1>;
197 interrupts = <0 43 1>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_i2c2>;
200 clocks = <&iobus_clk>;
201 clock-frequency = <400000>;
205 compatible = "socionext,uniphier-i2c";
207 reg = <0x58580000 0x40>;
208 #address-cells = <1>;
210 interrupts = <0 44 1>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_i2c3>;
213 clocks = <&iobus_clk>;
214 clock-frequency = <100000>;
218 compatible = "socionext,uniphier-sdhc";
220 reg = <0x5a400000 0x200>;
221 interrupts = <0 76 4>;
222 pinctrl-names = "default", "1.8v";
223 pinctrl-0 = <&pinctrl_sd>;
224 pinctrl-1 = <&pinctrl_sd_1v8>;
225 clocks = <&mio_clk 0>;
229 emmc: sdhc@5a500000 {
230 compatible = "socionext,uniphier-sdhc";
232 interrupts = <0 78 4>;
233 reg = <0x5a500000 0x200>;
234 pinctrl-names = "default", "1.8v";
235 pinctrl-0 = <&pinctrl_emmc>;
236 pinctrl-1 = <&pinctrl_emmc_1v8>;
237 clocks = <&mio_clk 1>;
243 compatible = "socionext,uniphier-ehci", "generic-ehci";
245 reg = <0x5a800100 0x100>;
246 interrupts = <0 80 4>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_usb0>;
249 clocks = <&mio_clk 3>, <&mio_clk 6>;
253 compatible = "socionext,uniphier-ehci", "generic-ehci";
255 reg = <0x5a810100 0x100>;
256 interrupts = <0 81 4>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_usb1>;
259 clocks = <&mio_clk 4>, <&mio_clk 6>;
263 compatible = "socionext,uniphier-ehci", "generic-ehci";
265 reg = <0x5a820100 0x100>;
266 interrupts = <0 82 4>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_usb2>;
269 clocks = <&mio_clk 5>, <&mio_clk 6>;
273 compatible = "simple-mfd", "syscon";
274 reg = <0x61830000 0x200>;
279 clock-frequency = <25000000>;
283 clock-frequency = <80000000>;
287 clock-frequency = <80000000>;
291 clock-frequency = <80000000>;
295 interrupts = <0 29 4>;
296 clock-frequency = <80000000>;
300 compatible = "socionext,uniphier-sld8-mio-clock";
304 compatible = "socionext,uniphier-sld8-mio-reset";
308 compatible = "socionext,uniphier-sld8-peri-clock";
312 compatible = "socionext,uniphier-sld8-peri-reset";
316 compatible = "socionext,uniphier-sld8-pinctrl";
320 compatible = "socionext,uniphier-sld8-clock";
324 compatible = "socionext,uniphier-sld8-reset";