2 * Device Tree Source for UniPhier PH1-sLD8 SoC
4 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+ X11
9 /include/ "skeleton.dtsi"
12 compatible = "socionext,ph1-sld8";
20 compatible = "arm,cortex-a9";
26 arm_timer_clk: arm_timer_clk {
28 compatible = "fixed-clock";
29 clock-frequency = <50000000>;
34 compatible = "fixed-clock";
35 clock-frequency = <80000000>;
38 iobus_clk: iobus_clk {
40 compatible = "fixed-clock";
41 clock-frequency = <100000000>;
46 compatible = "simple-bus";
50 interrupt-parent = <&intc>;
53 compatible = "simple-bus";
58 serial0: serial@54006800 {
59 compatible = "socionext,uniphier-uart";
61 reg = <0x54006800 0x40>;
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_uart0>;
64 interrupts = <0 33 4>;
66 clock-frequency = <80000000>;
69 serial1: serial@54006900 {
70 compatible = "socionext,uniphier-uart";
72 reg = <0x54006900 0x40>;
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_uart1>;
75 interrupts = <0 35 4>;
77 clock-frequency = <80000000>;
80 serial2: serial@54006a00 {
81 compatible = "socionext,uniphier-uart";
83 reg = <0x54006a00 0x40>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_uart2>;
86 interrupts = <0 37 4>;
88 clock-frequency = <80000000>;
91 serial3: serial@54006b00 {
92 compatible = "socionext,uniphier-uart";
94 reg = <0x54006b00 0x40>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_uart3>;
97 interrupts = <0 29 4>;
99 clock-frequency = <80000000>;
103 compatible = "socionext,uniphier-i2c";
105 reg = <0x58400000 0x40>;
106 #address-cells = <1>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_i2c0>;
110 interrupts = <0 41 1>;
111 clocks = <&iobus_clk>;
112 clock-frequency = <100000>;
116 compatible = "socionext,uniphier-i2c";
118 reg = <0x58480000 0x40>;
119 #address-cells = <1>;
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_i2c1>;
123 interrupts = <0 42 1>;
124 clocks = <&iobus_clk>;
125 clock-frequency = <100000>;
128 /* chip-internal connection for DMD */
130 compatible = "socionext,uniphier-i2c";
131 reg = <0x58500000 0x40>;
132 #address-cells = <1>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_i2c2>;
136 interrupts = <0 43 1>;
137 clocks = <&iobus_clk>;
138 clock-frequency = <400000>;
142 compatible = "socionext,uniphier-i2c";
144 reg = <0x58580000 0x40>;
145 #address-cells = <1>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_i2c3>;
149 interrupts = <0 44 1>;
150 clocks = <&iobus_clk>;
151 clock-frequency = <100000>;
154 system-bus-controller-misc@59800000 {
155 compatible = "socionext,uniphier-system-bus-controller-misc",
157 reg = <0x59800000 0x2000>;
161 compatible = "socionext,uniphier-ehci", "generic-ehci";
163 reg = <0x5a800100 0x100>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_usb0>;
166 interrupts = <0 80 4>;
170 compatible = "socionext,uniphier-ehci", "generic-ehci";
172 reg = <0x5a810100 0x100>;
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_usb1>;
175 interrupts = <0 81 4>;
179 compatible = "socionext,uniphier-ehci", "generic-ehci";
181 reg = <0x5a820100 0x100>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_usb2>;
184 interrupts = <0 82 4>;
187 pinctrl: pinctrl@5f801000 {
188 compatible = "socionext,ph1-sld8-pinctrl",
190 reg = <0x5f801000 0xe00>;
194 compatible = "arm,cortex-a9-global-timer";
195 reg = <0x60000200 0x20>;
196 interrupts = <1 11 0x104>;
197 clocks = <&arm_timer_clk>;
201 compatible = "arm,cortex-a9-twd-timer";
202 reg = <0x60000600 0x20>;
203 interrupts = <1 13 0x104>;
204 clocks = <&arm_timer_clk>;
207 intc: interrupt-controller@60001000 {
208 compatible = "arm,cortex-a9-gic";
209 #interrupt-cells = <3>;
210 interrupt-controller;
211 reg = <0x60001000 0x1000>,
215 nand: nand@68000000 {
216 compatible = "denali,denali-nand-dt";
217 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
218 reg-names = "nand_data", "denali_reg";
223 /include/ "uniphier-pinctrl.dtsi"