1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier SoCs default pinctrl settings
5 // Copyright (C) 2015-2017 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
24 pinctrl_ainiec1: ainiec1 {
29 pinctrl_aout1: aout1 {
34 pinctrl_aout2: aout2 {
39 pinctrl_aout3: aout3 {
44 pinctrl_aoutiec1: aoutiec1 {
46 function = "aoutiec1";
49 pinctrl_aoutiec2: aoutiec2 {
51 function = "aoutiec2";
55 groups = "emmc", "emmc_dat8";
59 pinctrl_emmc_1v8: emmc-1v8 {
60 groups = "emmc", "emmc_dat8";
64 pinctrl_ether_mii: ether-mii {
66 function = "ether_mii";
69 pinctrl_ether_rgmii: ether-rgmii {
70 groups = "ether_rgmii";
71 function = "ether_rgmii";
74 pinctrl_ether_rmii: ether-rmii {
75 groups = "ether_rmii";
76 function = "ether_rmii";
79 pinctrl_ether1_rgmii: ether1-rgmii {
80 groups = "ether1_rgmii";
81 function = "ether1_rgmii";
84 pinctrl_ether1_rmii: ether1-rmii {
85 groups = "ether1_rmii";
86 function = "ether1_rmii";
119 pinctrl_nand2cs: nand2cs {
120 groups = "nand", "nand_cs1";
129 pinctrl_sd_1v8: sd-1v8 {
139 pinctrl_sd1_1v8: sd1-1v8 {
144 pinctrl_system_bus: system-bus {
145 groups = "system_bus", "system_bus_cs1";
146 function = "system_bus";
149 pinctrl_uart0: uart0 {
154 pinctrl_uart1: uart1 {
159 pinctrl_uart2: uart2 {
164 pinctrl_uart3: uart3 {