]> git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-pro4.dtsi
rockchip: dts: rk3399: update for spl require driver
[u-boot] / arch / arm / dts / uniphier-pro4.dtsi
1 /*
2  * Device Tree Source for UniPhier Pro4 SoC
3  *
4  * Copyright (C) 2015-2016 Socionext Inc.
5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+        X11
8  */
9
10 / {
11         compatible = "socionext,uniphier-pro4";
12         #address-cells = <1>;
13         #size-cells = <1>;
14
15         cpus {
16                 #address-cells = <1>;
17                 #size-cells = <0>;
18
19                 cpu@0 {
20                         device_type = "cpu";
21                         compatible = "arm,cortex-a9";
22                         reg = <0>;
23                         enable-method = "psci";
24                         next-level-cache = <&l2>;
25                 };
26
27                 cpu@1 {
28                         device_type = "cpu";
29                         compatible = "arm,cortex-a9";
30                         reg = <1>;
31                         enable-method = "psci";
32                         next-level-cache = <&l2>;
33                 };
34         };
35
36         psci {
37                 compatible = "arm,psci-0.2";
38                 method = "smc";
39         };
40
41         clocks {
42                 refclk: ref {
43                         compatible = "fixed-clock";
44                         #clock-cells = <0>;
45                         clock-frequency = <25000000>;
46                 };
47
48                 arm_timer_clk: arm_timer_clk {
49                         #clock-cells = <0>;
50                         compatible = "fixed-clock";
51                         clock-frequency = <50000000>;
52                 };
53         };
54
55         soc {
56                 compatible = "simple-bus";
57                 #address-cells = <1>;
58                 #size-cells = <1>;
59                 ranges;
60                 interrupt-parent = <&intc>;
61                 u-boot,dm-pre-reloc;
62
63                 l2: l2-cache@500c0000 {
64                         compatible = "socionext,uniphier-system-cache";
65                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
66                               <0x506c0000 0x400>;
67                         interrupts = <0 174 4>, <0 175 4>;
68                         cache-unified;
69                         cache-size = <(768 * 1024)>;
70                         cache-sets = <256>;
71                         cache-line-size = <128>;
72                         cache-level = <2>;
73                 };
74
75                 serial0: serial@54006800 {
76                         compatible = "socionext,uniphier-uart";
77                         status = "disabled";
78                         reg = <0x54006800 0x40>;
79                         interrupts = <0 33 4>;
80                         pinctrl-names = "default";
81                         pinctrl-0 = <&pinctrl_uart0>;
82                         clocks = <&peri_clk 0>;
83                         clock-frequency = <73728000>;
84                 };
85
86                 serial1: serial@54006900 {
87                         compatible = "socionext,uniphier-uart";
88                         status = "disabled";
89                         reg = <0x54006900 0x40>;
90                         interrupts = <0 35 4>;
91                         pinctrl-names = "default";
92                         pinctrl-0 = <&pinctrl_uart1>;
93                         clocks = <&peri_clk 1>;
94                         clock-frequency = <73728000>;
95                 };
96
97                 serial2: serial@54006a00 {
98                         compatible = "socionext,uniphier-uart";
99                         status = "disabled";
100                         reg = <0x54006a00 0x40>;
101                         interrupts = <0 37 4>;
102                         pinctrl-names = "default";
103                         pinctrl-0 = <&pinctrl_uart2>;
104                         clocks = <&peri_clk 2>;
105                         clock-frequency = <73728000>;
106                 };
107
108                 serial3: serial@54006b00 {
109                         compatible = "socionext,uniphier-uart";
110                         status = "disabled";
111                         reg = <0x54006b00 0x40>;
112                         interrupts = <0 177 4>;
113                         pinctrl-names = "default";
114                         pinctrl-0 = <&pinctrl_uart3>;
115                         clocks = <&peri_clk 3>;
116                         clock-frequency = <73728000>;
117                 };
118
119                 port0x: gpio@55000008 {
120                         compatible = "socionext,uniphier-gpio";
121                         reg = <0x55000008 0x8>;
122                         gpio-controller;
123                         #gpio-cells = <2>;
124                 };
125
126                 port1x: gpio@55000010 {
127                         compatible = "socionext,uniphier-gpio";
128                         reg = <0x55000010 0x8>;
129                         gpio-controller;
130                         #gpio-cells = <2>;
131                 };
132
133                 port2x: gpio@55000018 {
134                         compatible = "socionext,uniphier-gpio";
135                         reg = <0x55000018 0x8>;
136                         gpio-controller;
137                         #gpio-cells = <2>;
138                 };
139
140                 port3x: gpio@55000020 {
141                         compatible = "socionext,uniphier-gpio";
142                         reg = <0x55000020 0x8>;
143                         gpio-controller;
144                         #gpio-cells = <2>;
145                 };
146
147                 port4: gpio@55000028 {
148                         compatible = "socionext,uniphier-gpio";
149                         reg = <0x55000028 0x8>;
150                         gpio-controller;
151                         #gpio-cells = <2>;
152                 };
153
154                 port5x: gpio@55000030 {
155                         compatible = "socionext,uniphier-gpio";
156                         reg = <0x55000030 0x8>;
157                         gpio-controller;
158                         #gpio-cells = <2>;
159                 };
160
161                 port6x: gpio@55000038 {
162                         compatible = "socionext,uniphier-gpio";
163                         reg = <0x55000038 0x8>;
164                         gpio-controller;
165                         #gpio-cells = <2>;
166                 };
167
168                 port7x: gpio@55000040 {
169                         compatible = "socionext,uniphier-gpio";
170                         reg = <0x55000040 0x8>;
171                         gpio-controller;
172                         #gpio-cells = <2>;
173                 };
174
175                 port8x: gpio@55000048 {
176                         compatible = "socionext,uniphier-gpio";
177                         reg = <0x55000048 0x8>;
178                         gpio-controller;
179                         #gpio-cells = <2>;
180                 };
181
182                 port9x: gpio@55000050 {
183                         compatible = "socionext,uniphier-gpio";
184                         reg = <0x55000050 0x8>;
185                         gpio-controller;
186                         #gpio-cells = <2>;
187                 };
188
189                 port10x: gpio@55000058 {
190                         compatible = "socionext,uniphier-gpio";
191                         reg = <0x55000058 0x8>;
192                         gpio-controller;
193                         #gpio-cells = <2>;
194                 };
195
196                 port11x: gpio@55000060 {
197                         compatible = "socionext,uniphier-gpio";
198                         reg = <0x55000060 0x8>;
199                         gpio-controller;
200                         #gpio-cells = <2>;
201                 };
202
203                 port12x: gpio@55000068 {
204                         compatible = "socionext,uniphier-gpio";
205                         reg = <0x55000068 0x8>;
206                         gpio-controller;
207                         #gpio-cells = <2>;
208                 };
209
210                 port13x: gpio@55000070 {
211                         compatible = "socionext,uniphier-gpio";
212                         reg = <0x55000070 0x8>;
213                         gpio-controller;
214                         #gpio-cells = <2>;
215                 };
216
217                 port14x: gpio@55000078 {
218                         compatible = "socionext,uniphier-gpio";
219                         reg = <0x55000078 0x8>;
220                         gpio-controller;
221                         #gpio-cells = <2>;
222                 };
223
224                 port17x: gpio@550000a0 {
225                         compatible = "socionext,uniphier-gpio";
226                         reg = <0x550000a0 0x8>;
227                         gpio-controller;
228                         #gpio-cells = <2>;
229                 };
230
231                 port18x: gpio@550000a8 {
232                         compatible = "socionext,uniphier-gpio";
233                         reg = <0x550000a8 0x8>;
234                         gpio-controller;
235                         #gpio-cells = <2>;
236                 };
237
238                 port19x: gpio@550000b0 {
239                         compatible = "socionext,uniphier-gpio";
240                         reg = <0x550000b0 0x8>;
241                         gpio-controller;
242                         #gpio-cells = <2>;
243                 };
244
245                 port20x: gpio@550000b8 {
246                         compatible = "socionext,uniphier-gpio";
247                         reg = <0x550000b8 0x8>;
248                         gpio-controller;
249                         #gpio-cells = <2>;
250                 };
251
252                 port21x: gpio@550000c0 {
253                         compatible = "socionext,uniphier-gpio";
254                         reg = <0x550000c0 0x8>;
255                         gpio-controller;
256                         #gpio-cells = <2>;
257                 };
258
259                 port22x: gpio@550000c8 {
260                         compatible = "socionext,uniphier-gpio";
261                         reg = <0x550000c8 0x8>;
262                         gpio-controller;
263                         #gpio-cells = <2>;
264                 };
265
266                 port23x: gpio@550000d0 {
267                         compatible = "socionext,uniphier-gpio";
268                         reg = <0x550000d0 0x8>;
269                         gpio-controller;
270                         #gpio-cells = <2>;
271                 };
272
273                 port24x: gpio@550000d8 {
274                         compatible = "socionext,uniphier-gpio";
275                         reg = <0x550000d8 0x8>;
276                         gpio-controller;
277                         #gpio-cells = <2>;
278                 };
279
280                 port25x: gpio@550000e0 {
281                         compatible = "socionext,uniphier-gpio";
282                         reg = <0x550000e0 0x8>;
283                         gpio-controller;
284                         #gpio-cells = <2>;
285                 };
286
287                 port26x: gpio@550000e8 {
288                         compatible = "socionext,uniphier-gpio";
289                         reg = <0x550000e8 0x8>;
290                         gpio-controller;
291                         #gpio-cells = <2>;
292                 };
293
294                 port27x: gpio@550000f0 {
295                         compatible = "socionext,uniphier-gpio";
296                         reg = <0x550000f0 0x8>;
297                         gpio-controller;
298                         #gpio-cells = <2>;
299                 };
300
301                 port28x: gpio@550000f8 {
302                         compatible = "socionext,uniphier-gpio";
303                         reg = <0x550000f8 0x8>;
304                         gpio-controller;
305                         #gpio-cells = <2>;
306                 };
307
308                 port29x: gpio@55000100 {
309                         compatible = "socionext,uniphier-gpio";
310                         reg = <0x55000100 0x8>;
311                         gpio-controller;
312                         #gpio-cells = <2>;
313                 };
314
315                 port30x: gpio@55000108 {
316                         compatible = "socionext,uniphier-gpio";
317                         reg = <0x55000108 0x8>;
318                         gpio-controller;
319                         #gpio-cells = <2>;
320                 };
321
322                 i2c0: i2c@58780000 {
323                         compatible = "socionext,uniphier-fi2c";
324                         status = "disabled";
325                         reg = <0x58780000 0x80>;
326                         #address-cells = <1>;
327                         #size-cells = <0>;
328                         interrupts = <0 41 4>;
329                         pinctrl-names = "default";
330                         pinctrl-0 = <&pinctrl_i2c0>;
331                         clocks = <&peri_clk 4>;
332                         clock-frequency = <100000>;
333                 };
334
335                 i2c1: i2c@58781000 {
336                         compatible = "socionext,uniphier-fi2c";
337                         status = "disabled";
338                         reg = <0x58781000 0x80>;
339                         #address-cells = <1>;
340                         #size-cells = <0>;
341                         interrupts = <0 42 4>;
342                         pinctrl-names = "default";
343                         pinctrl-0 = <&pinctrl_i2c1>;
344                         clocks = <&peri_clk 5>;
345                         clock-frequency = <100000>;
346                 };
347
348                 i2c2: i2c@58782000 {
349                         compatible = "socionext,uniphier-fi2c";
350                         status = "disabled";
351                         reg = <0x58782000 0x80>;
352                         #address-cells = <1>;
353                         #size-cells = <0>;
354                         interrupts = <0 43 4>;
355                         pinctrl-names = "default";
356                         pinctrl-0 = <&pinctrl_i2c2>;
357                         clocks = <&peri_clk 6>;
358                         clock-frequency = <100000>;
359                 };
360
361                 i2c3: i2c@58783000 {
362                         compatible = "socionext,uniphier-fi2c";
363                         status = "disabled";
364                         reg = <0x58783000 0x80>;
365                         #address-cells = <1>;
366                         #size-cells = <0>;
367                         interrupts = <0 44 4>;
368                         pinctrl-names = "default";
369                         pinctrl-0 = <&pinctrl_i2c3>;
370                         clocks = <&peri_clk 7>;
371                         clock-frequency = <100000>;
372                 };
373
374                 /* i2c4 does not exist */
375
376                 /* chip-internal connection for DMD */
377                 i2c5: i2c@58785000 {
378                         compatible = "socionext,uniphier-fi2c";
379                         reg = <0x58785000 0x80>;
380                         #address-cells = <1>;
381                         #size-cells = <0>;
382                         interrupts = <0 25 4>;
383                         clocks = <&peri_clk 9>;
384                         clock-frequency = <400000>;
385                 };
386
387                 /* chip-internal connection for HDMI */
388                 i2c6: i2c@58786000 {
389                         compatible = "socionext,uniphier-fi2c";
390                         reg = <0x58786000 0x80>;
391                         #address-cells = <1>;
392                         #size-cells = <0>;
393                         interrupts = <0 26 4>;
394                         clocks = <&peri_clk 10>;
395                         clock-frequency = <400000>;
396                 };
397
398                 system_bus: system-bus@58c00000 {
399                         compatible = "socionext,uniphier-system-bus";
400                         status = "disabled";
401                         reg = <0x58c00000 0x400>;
402                         #address-cells = <2>;
403                         #size-cells = <1>;
404                         pinctrl-names = "default";
405                         pinctrl-0 = <&pinctrl_system_bus>;
406                 };
407
408                 smpctrl@59800000 {
409                         compatible = "socionext,uniphier-smpctrl";
410                         reg = <0x59801000 0x400>;
411                 };
412
413                 mioctrl@59810000 {
414                         compatible = "socionext,uniphier-pro4-mioctrl",
415                                      "simple-mfd", "syscon";
416                         reg = <0x59810000 0x800>;
417                         u-boot,dm-pre-reloc;
418
419                         mio_clk: clock {
420                                 compatible = "socionext,uniphier-pro4-mio-clock";
421                                 #clock-cells = <1>;
422                         };
423
424                         mio_rst: reset {
425                                 compatible = "socionext,uniphier-pro4-mio-reset";
426                                 #reset-cells = <1>;
427                         };
428                 };
429
430                 perictrl@59820000 {
431                         compatible = "socionext,uniphier-pro4-perictrl",
432                                      "simple-mfd", "syscon";
433                         reg = <0x59820000 0x200>;
434
435                         peri_clk: clock {
436                                 compatible = "socionext,uniphier-pro4-peri-clock";
437                                 #clock-cells = <1>;
438                         };
439
440                         peri_rst: reset {
441                                 compatible = "socionext,uniphier-pro4-peri-reset";
442                                 #reset-cells = <1>;
443                         };
444                 };
445
446                 sd: sdhc@5a400000 {
447                         compatible = "socionext,uniphier-sdhc";
448                         status = "disabled";
449                         reg = <0x5a400000 0x200>;
450                         interrupts = <0 76 4>;
451                         pinctrl-names = "default", "1.8v";
452                         pinctrl-0 = <&pinctrl_sd>;
453                         pinctrl-1 = <&pinctrl_sd_1v8>;
454                         clocks = <&mio_clk 0>;
455                         reset-names = "host", "bridge";
456                         resets = <&mio_rst 0>, <&mio_rst 3>;
457                         bus-width = <4>;
458                         cap-sd-highspeed;
459                         sd-uhs-sdr12;
460                         sd-uhs-sdr25;
461                         sd-uhs-sdr50;
462                 };
463
464                 emmc: sdhc@5a500000 {
465                         compatible = "socionext,uniphier-sdhc";
466                         status = "disabled";
467                         reg = <0x5a500000 0x200>;
468                         interrupts = <0 78 4>;
469                         pinctrl-names = "default", "1.8v";
470                         pinctrl-0 = <&pinctrl_emmc>;
471                         pinctrl-1 = <&pinctrl_emmc_1v8>;
472                         clocks = <&mio_clk 1>;
473                         reset-names = "host", "bridge";
474                         resets = <&mio_rst 1>, <&mio_rst 4>;
475                         bus-width = <8>;
476                         non-removable;
477                         cap-mmc-highspeed;
478                         cap-mmc-hw-reset;
479                 };
480
481                 sd1: sdhc@5a600000 {
482                         compatible = "socionext,uniphier-sdhc";
483                         status = "disabled";
484                         reg = <0x5a600000 0x200>;
485                         interrupts = <0 85 4>;
486                         pinctrl-names = "default", "1.8v";
487                         pinctrl-0 = <&pinctrl_sd1>;
488                         pinctrl-1 = <&pinctrl_sd1_1v8>;
489                         clocks = <&mio_clk 2>;
490                         resets = <&mio_rst 2>, <&mio_rst 5>;
491                         bus-width = <4>;
492                         cap-sd-highspeed;
493                         sd-uhs-sdr12;
494                         sd-uhs-sdr25;
495                         sd-uhs-sdr50;
496                 };
497
498                 usb2: usb@5a800100 {
499                         compatible = "socionext,uniphier-ehci", "generic-ehci";
500                         status = "disabled";
501                         reg = <0x5a800100 0x100>;
502                         interrupts = <0 80 4>;
503                         pinctrl-names = "default";
504                         pinctrl-0 = <&pinctrl_usb2>;
505                         clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
506                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
507                                  <&mio_rst 12>;
508                 };
509
510                 usb3: usb@5a810100 {
511                         compatible = "socionext,uniphier-ehci", "generic-ehci";
512                         status = "disabled";
513                         reg = <0x5a810100 0x100>;
514                         interrupts = <0 81 4>;
515                         pinctrl-names = "default";
516                         pinctrl-0 = <&pinctrl_usb3>;
517                         clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
518                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
519                                  <&mio_rst 13>;
520                 };
521
522                 soc-glue@5f800000 {
523                         compatible = "socionext,uniphier-pro4-soc-glue",
524                                      "simple-mfd", "syscon";
525                         reg = <0x5f800000 0x2000>;
526                         u-boot,dm-pre-reloc;
527
528                         pinctrl: pinctrl {
529                                 compatible = "socionext,uniphier-pro4-pinctrl";
530                                 u-boot,dm-pre-reloc;
531                         };
532                 };
533
534                 aidet@5fc20000 {
535                         compatible = "simple-mfd", "syscon";
536                         reg = <0x5fc20000 0x200>;
537                 };
538
539                 timer@60000200 {
540                         compatible = "arm,cortex-a9-global-timer";
541                         reg = <0x60000200 0x20>;
542                         interrupts = <1 11 0x304>;
543                         clocks = <&arm_timer_clk>;
544                 };
545
546                 timer@60000600 {
547                         compatible = "arm,cortex-a9-twd-timer";
548                         reg = <0x60000600 0x20>;
549                         interrupts = <1 13 0x304>;
550                         clocks = <&arm_timer_clk>;
551                 };
552
553                 intc: interrupt-controller@60001000 {
554                         compatible = "arm,cortex-a9-gic";
555                         reg = <0x60001000 0x1000>,
556                               <0x60000100 0x100>;
557                         #interrupt-cells = <3>;
558                         interrupt-controller;
559                 };
560
561                 sysctrl@61840000 {
562                         compatible = "socionext,uniphier-pro4-sysctrl",
563                                      "simple-mfd", "syscon";
564                         reg = <0x61840000 0x10000>;
565
566                         sys_clk: clock {
567                                 compatible = "socionext,uniphier-pro4-clock";
568                                 #clock-cells = <1>;
569                         };
570
571                         sys_rst: reset {
572                                 compatible = "socionext,uniphier-pro4-reset";
573                                 #reset-cells = <1>;
574                         };
575                 };
576
577                 usb0: usb@65b00000 {
578                         compatible = "socionext,uniphier-pro4-dwc3";
579                         status = "disabled";
580                         reg = <0x65b00000 0x1000>;
581                         #address-cells = <1>;
582                         #size-cells = <1>;
583                         ranges;
584                         pinctrl-names = "default";
585                         pinctrl-0 = <&pinctrl_usb0>;
586                         dwc3@65a00000 {
587                                 compatible = "snps,dwc3";
588                                 reg = <0x65a00000 0x10000>;
589                                 interrupts = <0 134 4>;
590                                 tx-fifo-resize;
591                         };
592                 };
593
594                 usb1: usb@65d00000 {
595                         compatible = "socionext,uniphier-pro4-dwc3";
596                         status = "disabled";
597                         reg = <0x65d00000 0x1000>;
598                         #address-cells = <1>;
599                         #size-cells = <1>;
600                         ranges;
601                         pinctrl-names = "default";
602                         pinctrl-0 = <&pinctrl_usb1>;
603                         dwc3@65c00000 {
604                                 compatible = "snps,dwc3";
605                                 reg = <0x65c00000 0x10000>;
606                                 interrupts = <0 137 4>;
607                                 tx-fifo-resize;
608                         };
609                 };
610
611                 nand: nand@68000000 {
612                         compatible = "socionext,denali-nand-v5a";
613                         status = "disabled";
614                         reg-names = "nand_data", "denali_reg";
615                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
616                         interrupts = <0 65 4>;
617                         pinctrl-names = "default";
618                         pinctrl-0 = <&pinctrl_nand>;
619                         clocks = <&sys_clk 2>;
620                         nand-ecc-strength = <8>;
621                 };
622         };
623 };
624
625 /include/ "uniphier-pinctrl.dtsi"