2 * Device Tree Source for UniPhier Pro4 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
47 compatible = "socionext,uniphier-pro4";
57 compatible = "arm,cortex-a9";
59 enable-method = "psci";
60 next-level-cache = <&l2>;
65 compatible = "arm,cortex-a9";
67 enable-method = "psci";
68 next-level-cache = <&l2>;
73 compatible = "arm,psci-0.2";
79 compatible = "fixed-clock";
81 clock-frequency = <25000000>;
84 arm_timer_clk: arm_timer_clk {
86 compatible = "fixed-clock";
87 clock-frequency = <50000000>;
92 compatible = "simple-bus";
96 interrupt-parent = <&intc>;
99 l2: l2-cache@500c0000 {
100 compatible = "socionext,uniphier-system-cache";
101 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
103 interrupts = <0 174 4>, <0 175 4>;
105 cache-size = <(768 * 1024)>;
107 cache-line-size = <128>;
111 serial0: serial@54006800 {
112 compatible = "socionext,uniphier-uart";
114 reg = <0x54006800 0x40>;
115 interrupts = <0 33 4>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_uart0>;
118 clocks = <&peri_clk 0>;
119 clock-frequency = <73728000>;
122 serial1: serial@54006900 {
123 compatible = "socionext,uniphier-uart";
125 reg = <0x54006900 0x40>;
126 interrupts = <0 35 4>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_uart1>;
129 clocks = <&peri_clk 1>;
130 clock-frequency = <73728000>;
133 serial2: serial@54006a00 {
134 compatible = "socionext,uniphier-uart";
136 reg = <0x54006a00 0x40>;
137 interrupts = <0 37 4>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_uart2>;
140 clocks = <&peri_clk 2>;
141 clock-frequency = <73728000>;
144 serial3: serial@54006b00 {
145 compatible = "socionext,uniphier-uart";
147 reg = <0x54006b00 0x40>;
148 interrupts = <0 177 4>;
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_uart3>;
151 clocks = <&peri_clk 3>;
152 clock-frequency = <73728000>;
155 port0x: gpio@55000008 {
156 compatible = "socionext,uniphier-gpio";
157 reg = <0x55000008 0x8>;
162 port1x: gpio@55000010 {
163 compatible = "socionext,uniphier-gpio";
164 reg = <0x55000010 0x8>;
169 port2x: gpio@55000018 {
170 compatible = "socionext,uniphier-gpio";
171 reg = <0x55000018 0x8>;
176 port3x: gpio@55000020 {
177 compatible = "socionext,uniphier-gpio";
178 reg = <0x55000020 0x8>;
183 port4: gpio@55000028 {
184 compatible = "socionext,uniphier-gpio";
185 reg = <0x55000028 0x8>;
190 port5x: gpio@55000030 {
191 compatible = "socionext,uniphier-gpio";
192 reg = <0x55000030 0x8>;
197 port6x: gpio@55000038 {
198 compatible = "socionext,uniphier-gpio";
199 reg = <0x55000038 0x8>;
204 port7x: gpio@55000040 {
205 compatible = "socionext,uniphier-gpio";
206 reg = <0x55000040 0x8>;
211 port8x: gpio@55000048 {
212 compatible = "socionext,uniphier-gpio";
213 reg = <0x55000048 0x8>;
218 port9x: gpio@55000050 {
219 compatible = "socionext,uniphier-gpio";
220 reg = <0x55000050 0x8>;
225 port10x: gpio@55000058 {
226 compatible = "socionext,uniphier-gpio";
227 reg = <0x55000058 0x8>;
232 port11x: gpio@55000060 {
233 compatible = "socionext,uniphier-gpio";
234 reg = <0x55000060 0x8>;
239 port12x: gpio@55000068 {
240 compatible = "socionext,uniphier-gpio";
241 reg = <0x55000068 0x8>;
246 port13x: gpio@55000070 {
247 compatible = "socionext,uniphier-gpio";
248 reg = <0x55000070 0x8>;
253 port14x: gpio@55000078 {
254 compatible = "socionext,uniphier-gpio";
255 reg = <0x55000078 0x8>;
260 port17x: gpio@550000a0 {
261 compatible = "socionext,uniphier-gpio";
262 reg = <0x550000a0 0x8>;
267 port18x: gpio@550000a8 {
268 compatible = "socionext,uniphier-gpio";
269 reg = <0x550000a8 0x8>;
274 port19x: gpio@550000b0 {
275 compatible = "socionext,uniphier-gpio";
276 reg = <0x550000b0 0x8>;
281 port20x: gpio@550000b8 {
282 compatible = "socionext,uniphier-gpio";
283 reg = <0x550000b8 0x8>;
288 port21x: gpio@550000c0 {
289 compatible = "socionext,uniphier-gpio";
290 reg = <0x550000c0 0x8>;
295 port22x: gpio@550000c8 {
296 compatible = "socionext,uniphier-gpio";
297 reg = <0x550000c8 0x8>;
302 port23x: gpio@550000d0 {
303 compatible = "socionext,uniphier-gpio";
304 reg = <0x550000d0 0x8>;
309 port24x: gpio@550000d8 {
310 compatible = "socionext,uniphier-gpio";
311 reg = <0x550000d8 0x8>;
316 port25x: gpio@550000e0 {
317 compatible = "socionext,uniphier-gpio";
318 reg = <0x550000e0 0x8>;
323 port26x: gpio@550000e8 {
324 compatible = "socionext,uniphier-gpio";
325 reg = <0x550000e8 0x8>;
330 port27x: gpio@550000f0 {
331 compatible = "socionext,uniphier-gpio";
332 reg = <0x550000f0 0x8>;
337 port28x: gpio@550000f8 {
338 compatible = "socionext,uniphier-gpio";
339 reg = <0x550000f8 0x8>;
344 port29x: gpio@55000100 {
345 compatible = "socionext,uniphier-gpio";
346 reg = <0x55000100 0x8>;
351 port30x: gpio@55000108 {
352 compatible = "socionext,uniphier-gpio";
353 reg = <0x55000108 0x8>;
359 compatible = "socionext,uniphier-fi2c";
361 reg = <0x58780000 0x80>;
362 #address-cells = <1>;
364 interrupts = <0 41 4>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_i2c0>;
367 clocks = <&peri_clk 4>;
368 clock-frequency = <100000>;
372 compatible = "socionext,uniphier-fi2c";
374 reg = <0x58781000 0x80>;
375 #address-cells = <1>;
377 interrupts = <0 42 4>;
378 pinctrl-names = "default";
379 pinctrl-0 = <&pinctrl_i2c1>;
380 clocks = <&peri_clk 5>;
381 clock-frequency = <100000>;
385 compatible = "socionext,uniphier-fi2c";
387 reg = <0x58782000 0x80>;
388 #address-cells = <1>;
390 interrupts = <0 43 4>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_i2c2>;
393 clocks = <&peri_clk 6>;
394 clock-frequency = <100000>;
398 compatible = "socionext,uniphier-fi2c";
400 reg = <0x58783000 0x80>;
401 #address-cells = <1>;
403 interrupts = <0 44 4>;
404 pinctrl-names = "default";
405 pinctrl-0 = <&pinctrl_i2c3>;
406 clocks = <&peri_clk 7>;
407 clock-frequency = <100000>;
410 /* i2c4 does not exist */
412 /* chip-internal connection for DMD */
414 compatible = "socionext,uniphier-fi2c";
415 reg = <0x58785000 0x80>;
416 #address-cells = <1>;
418 interrupts = <0 25 4>;
419 clocks = <&peri_clk 9>;
420 clock-frequency = <400000>;
423 /* chip-internal connection for HDMI */
425 compatible = "socionext,uniphier-fi2c";
426 reg = <0x58786000 0x80>;
427 #address-cells = <1>;
429 interrupts = <0 26 4>;
430 clocks = <&peri_clk 10>;
431 clock-frequency = <400000>;
434 system_bus: system-bus@58c00000 {
435 compatible = "socionext,uniphier-system-bus";
437 reg = <0x58c00000 0x400>;
438 #address-cells = <2>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_system_bus>;
445 compatible = "socionext,uniphier-smpctrl";
446 reg = <0x59801000 0x400>;
450 compatible = "socionext,uniphier-pro4-mioctrl",
451 "simple-mfd", "syscon";
452 reg = <0x59810000 0x800>;
456 compatible = "socionext,uniphier-pro4-mio-clock";
461 compatible = "socionext,uniphier-pro4-mio-reset";
467 compatible = "socionext,uniphier-pro4-perictrl",
468 "simple-mfd", "syscon";
469 reg = <0x59820000 0x200>;
472 compatible = "socionext,uniphier-pro4-peri-clock";
477 compatible = "socionext,uniphier-pro4-peri-reset";
483 compatible = "socionext,uniphier-sdhc";
485 reg = <0x5a400000 0x200>;
486 interrupts = <0 76 4>;
487 pinctrl-names = "default", "1.8v";
488 pinctrl-0 = <&pinctrl_sd>;
489 pinctrl-1 = <&pinctrl_sd_1v8>;
490 clocks = <&mio_clk 0>;
491 reset-names = "host", "bridge";
492 resets = <&mio_rst 0>, <&mio_rst 3>;
500 emmc: sdhc@5a500000 {
501 compatible = "socionext,uniphier-sdhc";
503 reg = <0x5a500000 0x200>;
504 interrupts = <0 78 4>;
505 pinctrl-names = "default", "1.8v";
506 pinctrl-0 = <&pinctrl_emmc>;
507 pinctrl-1 = <&pinctrl_emmc_1v8>;
508 clocks = <&mio_clk 1>;
509 reset-names = "host", "bridge";
510 resets = <&mio_rst 1>, <&mio_rst 4>;
518 compatible = "socionext,uniphier-sdhc";
520 reg = <0x5a600000 0x200>;
521 interrupts = <0 85 4>;
522 pinctrl-names = "default", "1.8v";
523 pinctrl-0 = <&pinctrl_sd1>;
524 pinctrl-1 = <&pinctrl_sd1_1v8>;
525 clocks = <&mio_clk 2>;
526 resets = <&mio_rst 2>, <&mio_rst 5>;
535 compatible = "socionext,uniphier-ehci", "generic-ehci";
537 reg = <0x5a800100 0x100>;
538 interrupts = <0 80 4>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&pinctrl_usb2>;
541 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
542 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
547 compatible = "socionext,uniphier-ehci", "generic-ehci";
549 reg = <0x5a810100 0x100>;
550 interrupts = <0 81 4>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&pinctrl_usb3>;
553 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
554 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
559 compatible = "socionext,uniphier-pro4-soc-glue",
560 "simple-mfd", "syscon";
561 reg = <0x5f800000 0x2000>;
565 compatible = "socionext,uniphier-pro4-pinctrl";
571 compatible = "simple-mfd", "syscon";
572 reg = <0x5fc20000 0x200>;
576 compatible = "arm,cortex-a9-global-timer";
577 reg = <0x60000200 0x20>;
578 interrupts = <1 11 0x304>;
579 clocks = <&arm_timer_clk>;
583 compatible = "arm,cortex-a9-twd-timer";
584 reg = <0x60000600 0x20>;
585 interrupts = <1 13 0x304>;
586 clocks = <&arm_timer_clk>;
589 intc: interrupt-controller@60001000 {
590 compatible = "arm,cortex-a9-gic";
591 reg = <0x60001000 0x1000>,
593 #interrupt-cells = <3>;
594 interrupt-controller;
598 compatible = "socionext,uniphier-pro4-sysctrl",
599 "simple-mfd", "syscon";
600 reg = <0x61840000 0x10000>;
603 compatible = "socionext,uniphier-pro4-clock";
608 compatible = "socionext,uniphier-pro4-reset";
614 compatible = "socionext,uniphier-pro4-dwc3";
616 reg = <0x65b00000 0x1000>;
617 #address-cells = <1>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&pinctrl_usb0>;
623 compatible = "snps,dwc3";
624 reg = <0x65a00000 0x10000>;
625 interrupts = <0 134 4>;
631 compatible = "socionext,uniphier-pro4-dwc3";
633 reg = <0x65d00000 0x1000>;
634 #address-cells = <1>;
637 pinctrl-names = "default";
638 pinctrl-0 = <&pinctrl_usb1>;
640 compatible = "snps,dwc3";
641 reg = <0x65c00000 0x10000>;
642 interrupts = <0 137 4>;
647 nand: nand@68000000 {
648 compatible = "socionext,uniphier-denali-nand-v5a";
650 reg-names = "nand_data", "denali_reg";
651 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
652 interrupts = <0 65 4>;
653 pinctrl-names = "default";
654 pinctrl-0 = <&pinctrl_nand>;
655 clocks = <&sys_clk 2>;
656 nand-ecc-strength = <8>;
661 /include/ "uniphier-pinctrl.dtsi"