git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-pro4.dtsi

   1 /*
   2  * Device Tree Source for UniPhier Pro4 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 / {
  11         compatible = "socionext,uniphier-pro4";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         enable-method = "psci";
  24                         next-level-cache = <&l2>;
  25                 };
  26
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a9";
  30                         reg = <1>;
  31                         enable-method = "psci";
  32                         next-level-cache = <&l2>;
  33                 };
  34         };
  35
  36         psci {
  37                 compatible = "arm,psci-0.2";
  38                 method = "smc";
  39         };
  40
  41         clocks {
  42                 refclk: ref {
  43                         compatible = "fixed-clock";
  44                         #clock-cells = <0>;
  45                         clock-frequency = <25000000>;
  46                 };
  47
  48                 arm_timer_clk: arm_timer_clk {
  49                         #clock-cells = <0>;
  50                         compatible = "fixed-clock";
  51                         clock-frequency = <50000000>;
  52                 };
  53         };
  54
  55         soc {
  56                 compatible = "simple-bus";
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 ranges;
  60                 interrupt-parent = <&intc>;
  61
  62                 l2: l2-cache@500c0000 {
  63                         compatible = "socionext,uniphier-system-cache";
  64                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  65                               <0x506c0000 0x400>;
  66                         interrupts = <0 174 4>, <0 175 4>;
  67                         cache-unified;
  68                         cache-size = <(768 * 1024)>;
  69                         cache-sets = <256>;
  70                         cache-line-size = <128>;
  71                         cache-level = <2>;
  72                 };
  73
  74                 serial0: serial@54006800 {
  75                         compatible = "socionext,uniphier-uart";
  76                         status = "disabled";
  77                         reg = <0x54006800 0x40>;
  78                         interrupts = <0 33 4>;
  79                         pinctrl-names = "default";
  80                         pinctrl-0 = <&pinctrl_uart0>;
  81                         clocks = <&peri_clk 0>;
  82                         clock-frequency = <73728000>;
  83                 };
  84
  85                 serial1: serial@54006900 {
  86                         compatible = "socionext,uniphier-uart";
  87                         status = "disabled";
  88                         reg = <0x54006900 0x40>;
  89                         interrupts = <0 35 4>;
  90                         pinctrl-names = "default";
  91                         pinctrl-0 = <&pinctrl_uart1>;
  92                         clocks = <&peri_clk 1>;
  93                         clock-frequency = <73728000>;
  94                 };
  95
  96                 serial2: serial@54006a00 {
  97                         compatible = "socionext,uniphier-uart";
  98                         status = "disabled";
  99                         reg = <0x54006a00 0x40>;
 100                         interrupts = <0 37 4>;
 101                         pinctrl-names = "default";
 102                         pinctrl-0 = <&pinctrl_uart2>;
 103                         clocks = <&peri_clk 2>;
 104                         clock-frequency = <73728000>;
 105                 };
 106
 107                 serial3: serial@54006b00 {
 108                         compatible = "socionext,uniphier-uart";
 109                         status = "disabled";
 110                         reg = <0x54006b00 0x40>;
 111                         interrupts = <0 177 4>;
 112                         pinctrl-names = "default";
 113                         pinctrl-0 = <&pinctrl_uart3>;
 114                         clocks = <&peri_clk 3>;
 115                         clock-frequency = <73728000>;
 116                 };
 117
 118                 gpio: gpio@55000000 {
 119                         compatible = "socionext,uniphier-gpio";
 120                         reg = <0x55000000 0x200>;
 121                         interrupt-parent = <&aidet>;
 122                         interrupt-controller;
 123                         #interrupt-cells = <2>;
 124                         gpio-controller;
 125                         #gpio-cells = <2>;
 126                         gpio-ranges = <&pinctrl 0 0 0>;
 127                         gpio-ranges-group-names = "gpio_range";
 128                         ngpios = <248>;
 129                 };
 130
 131                 i2c0: i2c@58780000 {
 132                         compatible = "socionext,uniphier-fi2c";
 133                         status = "disabled";
 134                         reg = <0x58780000 0x80>;
 135                         #address-cells = <1>;
 136                         #size-cells = <0>;
 137                         interrupts = <0 41 4>;
 138                         pinctrl-names = "default";
 139                         pinctrl-0 = <&pinctrl_i2c0>;
 140                         clocks = <&peri_clk 4>;
 141                         clock-frequency = <100000>;
 142                 };
 143
 144                 i2c1: i2c@58781000 {
 145                         compatible = "socionext,uniphier-fi2c";
 146                         status = "disabled";
 147                         reg = <0x58781000 0x80>;
 148                         #address-cells = <1>;
 149                         #size-cells = <0>;
 150                         interrupts = <0 42 4>;
 151                         pinctrl-names = "default";
 152                         pinctrl-0 = <&pinctrl_i2c1>;
 153                         clocks = <&peri_clk 5>;
 154                         clock-frequency = <100000>;
 155                 };
 156
 157                 i2c2: i2c@58782000 {
 158                         compatible = "socionext,uniphier-fi2c";
 159                         status = "disabled";
 160                         reg = <0x58782000 0x80>;
 161                         #address-cells = <1>;
 162                         #size-cells = <0>;
 163                         interrupts = <0 43 4>;
 164                         pinctrl-names = "default";
 165                         pinctrl-0 = <&pinctrl_i2c2>;
 166                         clocks = <&peri_clk 6>;
 167                         clock-frequency = <100000>;
 168                 };
 169
 170                 i2c3: i2c@58783000 {
 171                         compatible = "socionext,uniphier-fi2c";
 172                         status = "disabled";
 173                         reg = <0x58783000 0x80>;
 174                         #address-cells = <1>;
 175                         #size-cells = <0>;
 176                         interrupts = <0 44 4>;
 177                         pinctrl-names = "default";
 178                         pinctrl-0 = <&pinctrl_i2c3>;
 179                         clocks = <&peri_clk 7>;
 180                         clock-frequency = <100000>;
 181                 };
 182
 183                 /* i2c4 does not exist */
 184
 185                 /* chip-internal connection for DMD */
 186                 i2c5: i2c@58785000 {
 187                         compatible = "socionext,uniphier-fi2c";
 188                         reg = <0x58785000 0x80>;
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         interrupts = <0 25 4>;
 192                         clocks = <&peri_clk 9>;
 193                         clock-frequency = <400000>;
 194                 };
 195
 196                 /* chip-internal connection for HDMI */
 197                 i2c6: i2c@58786000 {
 198                         compatible = "socionext,uniphier-fi2c";
 199                         reg = <0x58786000 0x80>;
 200                         #address-cells = <1>;
 201                         #size-cells = <0>;
 202                         interrupts = <0 26 4>;
 203                         clocks = <&peri_clk 10>;
 204                         clock-frequency = <400000>;
 205                 };
 206
 207                 system_bus: system-bus@58c00000 {
 208                         compatible = "socionext,uniphier-system-bus";
 209                         status = "disabled";
 210                         reg = <0x58c00000 0x400>;
 211                         #address-cells = <2>;
 212                         #size-cells = <1>;
 213                         pinctrl-names = "default";
 214                         pinctrl-0 = <&pinctrl_system_bus>;
 215                 };
 216
 217                 smpctrl@59801000 {
 218                         compatible = "socionext,uniphier-smpctrl";
 219                         reg = <0x59801000 0x400>;
 220                 };
 221
 222                 mioctrl@59810000 {
 223                         compatible = "socionext,uniphier-pro4-mioctrl",
 224                                      "simple-mfd", "syscon";
 225                         reg = <0x59810000 0x800>;
 226
 227                         mio_clk: clock {
 228                                 compatible = "socionext,uniphier-pro4-mio-clock";
 229                                 #clock-cells = <1>;
 230                         };
 231
 232                         mio_rst: reset {
 233                                 compatible = "socionext,uniphier-pro4-mio-reset";
 234                                 #reset-cells = <1>;
 235                         };
 236                 };
 237
 238                 perictrl@59820000 {
 239                         compatible = "socionext,uniphier-pro4-perictrl",
 240                                      "simple-mfd", "syscon";
 241                         reg = <0x59820000 0x200>;
 242
 243                         peri_clk: clock {
 244                                 compatible = "socionext,uniphier-pro4-peri-clock";
 245                                 #clock-cells = <1>;
 246                         };
 247
 248                         peri_rst: reset {
 249                                 compatible = "socionext,uniphier-pro4-peri-reset";
 250                                 #reset-cells = <1>;
 251                         };
 252                 };
 253
 254                 sd: sdhc@5a400000 {
 255                         compatible = "socionext,uniphier-sdhc";
 256                         status = "disabled";
 257                         reg = <0x5a400000 0x200>;
 258                         interrupts = <0 76 4>;
 259                         pinctrl-names = "default", "1.8v";
 260                         pinctrl-0 = <&pinctrl_sd>;
 261                         pinctrl-1 = <&pinctrl_sd_1v8>;
 262                         clocks = <&mio_clk 0>;
 263                         reset-names = "host", "bridge";
 264                         resets = <&mio_rst 0>, <&mio_rst 3>;
 265                         bus-width = <4>;
 266                         cap-sd-highspeed;
 267                         sd-uhs-sdr12;
 268                         sd-uhs-sdr25;
 269                         sd-uhs-sdr50;
 270                 };
 271
 272                 emmc: sdhc@5a500000 {
 273                         compatible = "socionext,uniphier-sdhc";
 274                         status = "disabled";
 275                         reg = <0x5a500000 0x200>;
 276                         interrupts = <0 78 4>;
 277                         pinctrl-names = "default", "1.8v";
 278                         pinctrl-0 = <&pinctrl_emmc>;
 279                         pinctrl-1 = <&pinctrl_emmc_1v8>;
 280                         clocks = <&mio_clk 1>;
 281                         reset-names = "host", "bridge";
 282                         resets = <&mio_rst 1>, <&mio_rst 4>;
 283                         bus-width = <8>;
 284                         non-removable;
 285                         cap-mmc-highspeed;
 286                         cap-mmc-hw-reset;
 287                 };
 288
 289                 sd1: sdhc@5a600000 {
 290                         compatible = "socionext,uniphier-sdhc";
 291                         status = "disabled";
 292                         reg = <0x5a600000 0x200>;
 293                         interrupts = <0 85 4>;
 294                         pinctrl-names = "default", "1.8v";
 295                         pinctrl-0 = <&pinctrl_sd1>;
 296                         pinctrl-1 = <&pinctrl_sd1_1v8>;
 297                         clocks = <&mio_clk 2>;
 298                         resets = <&mio_rst 2>, <&mio_rst 5>;
 299                         bus-width = <4>;
 300                         cap-sd-highspeed;
 301                         sd-uhs-sdr12;
 302                         sd-uhs-sdr25;
 303                         sd-uhs-sdr50;
 304                 };
 305
 306                 usb2: usb@5a800100 {
 307                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 308                         status = "disabled";
 309                         reg = <0x5a800100 0x100>;
 310                         interrupts = <0 80 4>;
 311                         pinctrl-names = "default";
 312                         pinctrl-0 = <&pinctrl_usb2>;
 313                         clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
 314                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 315                                  <&mio_rst 12>;
 316                 };
 317
 318                 usb3: usb@5a810100 {
 319                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 320                         status = "disabled";
 321                         reg = <0x5a810100 0x100>;
 322                         interrupts = <0 81 4>;
 323                         pinctrl-names = "default";
 324                         pinctrl-0 = <&pinctrl_usb3>;
 325                         clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
 326                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 327                                  <&mio_rst 13>;
 328                 };
 329
 330                 soc-glue@5f800000 {
 331                         compatible = "socionext,uniphier-pro4-soc-glue",
 332                                      "simple-mfd", "syscon";
 333                         reg = <0x5f800000 0x2000>;
 334
 335                         pinctrl: pinctrl {
 336                                 compatible = "socionext,uniphier-pro4-pinctrl";
 337                         };
 338                 };
 339
 340                 aidet: aidet@5fc20000 {
 341                         compatible = "socionext,uniphier-pro4-aidet";
 342                         reg = <0x5fc20000 0x200>;
 343                         interrupt-controller;
 344                         #interrupt-cells = <2>;
 345                 };
 346
 347                 timer@60000200 {
 348                         compatible = "arm,cortex-a9-global-timer";
 349                         reg = <0x60000200 0x20>;
 350                         interrupts = <1 11 0x304>;
 351                         clocks = <&arm_timer_clk>;
 352                 };
 353
 354                 timer@60000600 {
 355                         compatible = "arm,cortex-a9-twd-timer";
 356                         reg = <0x60000600 0x20>;
 357                         interrupts = <1 13 0x304>;
 358                         clocks = <&arm_timer_clk>;
 359                 };
 360
 361                 intc: interrupt-controller@60001000 {
 362                         compatible = "arm,cortex-a9-gic";
 363                         reg = <0x60001000 0x1000>,
 364                               <0x60000100 0x100>;
 365                         #interrupt-cells = <3>;
 366                         interrupt-controller;
 367                 };
 368
 369                 sysctrl@61840000 {
 370                         compatible = "socionext,uniphier-pro4-sysctrl",
 371                                      "simple-mfd", "syscon";
 372                         reg = <0x61840000 0x10000>;
 373
 374                         sys_clk: clock {
 375                                 compatible = "socionext,uniphier-pro4-clock";
 376                                 #clock-cells = <1>;
 377                         };
 378
 379                         sys_rst: reset {
 380                                 compatible = "socionext,uniphier-pro4-reset";
 381                                 #reset-cells = <1>;
 382                         };
 383                 };
 384
 385                 usb0: usb@65b00000 {
 386                         compatible = "socionext,uniphier-pro4-dwc3";
 387                         status = "disabled";
 388                         reg = <0x65b00000 0x1000>;
 389                         #address-cells = <1>;
 390                         #size-cells = <1>;
 391                         ranges;
 392                         pinctrl-names = "default";
 393                         pinctrl-0 = <&pinctrl_usb0>;
 394                         dwc3@65a00000 {
 395                                 compatible = "snps,dwc3";
 396                                 reg = <0x65a00000 0x10000>;
 397                                 interrupts = <0 134 4>;
 398                                 dr_mode = "host";
 399                                 tx-fifo-resize;
 400                         };
 401                 };
 402
 403                 usb1: usb@65d00000 {
 404                         compatible = "socionext,uniphier-pro4-dwc3";
 405                         status = "disabled";
 406                         reg = <0x65d00000 0x1000>;
 407                         #address-cells = <1>;
 408                         #size-cells = <1>;
 409                         ranges;
 410                         pinctrl-names = "default";
 411                         pinctrl-0 = <&pinctrl_usb1>;
 412                         dwc3@65c00000 {
 413                                 compatible = "snps,dwc3";
 414                                 reg = <0x65c00000 0x10000>;
 415                                 interrupts = <0 137 4>;
 416                                 dr_mode = "host";
 417                                 tx-fifo-resize;
 418                         };
 419                 };
 420
 421                 nand: nand@68000000 {
 422                         compatible = "socionext,uniphier-denali-nand-v5a";
 423                         status = "disabled";
 424                         reg-names = "nand_data", "denali_reg";
 425                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 426                         interrupts = <0 65 4>;
 427                         pinctrl-names = "default";
 428                         pinctrl-0 = <&pinctrl_nand>;
 429                         clocks = <&sys_clk 2>;
 430                 };
 431         };
 432 };
 433
 434 #include "uniphier-pinctrl.dtsi"