2 * Device Tree Source for UniPhier Pro4 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-pro4";
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
29 compatible = "arm,cortex-a9";
31 enable-method = "psci";
32 next-level-cache = <&l2>;
37 compatible = "arm,psci-0.2";
43 compatible = "fixed-clock";
45 clock-frequency = <25000000>;
48 arm_timer_clk: arm_timer_clk {
50 compatible = "fixed-clock";
51 clock-frequency = <50000000>;
56 compatible = "simple-bus";
60 interrupt-parent = <&intc>;
63 l2: l2-cache@500c0000 {
64 compatible = "socionext,uniphier-system-cache";
65 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
67 interrupts = <0 174 4>, <0 175 4>;
69 cache-size = <(768 * 1024)>;
71 cache-line-size = <128>;
75 serial0: serial@54006800 {
76 compatible = "socionext,uniphier-uart";
78 reg = <0x54006800 0x40>;
79 interrupts = <0 33 4>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_uart0>;
82 clocks = <&peri_clk 0>;
83 clock-frequency = <73728000>;
86 serial1: serial@54006900 {
87 compatible = "socionext,uniphier-uart";
89 reg = <0x54006900 0x40>;
90 interrupts = <0 35 4>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_uart1>;
93 clocks = <&peri_clk 1>;
94 clock-frequency = <73728000>;
97 serial2: serial@54006a00 {
98 compatible = "socionext,uniphier-uart";
100 reg = <0x54006a00 0x40>;
101 interrupts = <0 37 4>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_uart2>;
104 clocks = <&peri_clk 2>;
105 clock-frequency = <73728000>;
108 serial3: serial@54006b00 {
109 compatible = "socionext,uniphier-uart";
111 reg = <0x54006b00 0x40>;
112 interrupts = <0 177 4>;
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_uart3>;
115 clocks = <&peri_clk 3>;
116 clock-frequency = <73728000>;
119 port0x: gpio@55000008 {
120 compatible = "socionext,uniphier-gpio";
121 reg = <0x55000008 0x8>;
126 port1x: gpio@55000010 {
127 compatible = "socionext,uniphier-gpio";
128 reg = <0x55000010 0x8>;
133 port2x: gpio@55000018 {
134 compatible = "socionext,uniphier-gpio";
135 reg = <0x55000018 0x8>;
140 port3x: gpio@55000020 {
141 compatible = "socionext,uniphier-gpio";
142 reg = <0x55000020 0x8>;
147 port4: gpio@55000028 {
148 compatible = "socionext,uniphier-gpio";
149 reg = <0x55000028 0x8>;
154 port5x: gpio@55000030 {
155 compatible = "socionext,uniphier-gpio";
156 reg = <0x55000030 0x8>;
161 port6x: gpio@55000038 {
162 compatible = "socionext,uniphier-gpio";
163 reg = <0x55000038 0x8>;
168 port7x: gpio@55000040 {
169 compatible = "socionext,uniphier-gpio";
170 reg = <0x55000040 0x8>;
175 port8x: gpio@55000048 {
176 compatible = "socionext,uniphier-gpio";
177 reg = <0x55000048 0x8>;
182 port9x: gpio@55000050 {
183 compatible = "socionext,uniphier-gpio";
184 reg = <0x55000050 0x8>;
189 port10x: gpio@55000058 {
190 compatible = "socionext,uniphier-gpio";
191 reg = <0x55000058 0x8>;
196 port11x: gpio@55000060 {
197 compatible = "socionext,uniphier-gpio";
198 reg = <0x55000060 0x8>;
203 port12x: gpio@55000068 {
204 compatible = "socionext,uniphier-gpio";
205 reg = <0x55000068 0x8>;
210 port13x: gpio@55000070 {
211 compatible = "socionext,uniphier-gpio";
212 reg = <0x55000070 0x8>;
217 port14x: gpio@55000078 {
218 compatible = "socionext,uniphier-gpio";
219 reg = <0x55000078 0x8>;
224 port17x: gpio@550000a0 {
225 compatible = "socionext,uniphier-gpio";
226 reg = <0x550000a0 0x8>;
231 port18x: gpio@550000a8 {
232 compatible = "socionext,uniphier-gpio";
233 reg = <0x550000a8 0x8>;
238 port19x: gpio@550000b0 {
239 compatible = "socionext,uniphier-gpio";
240 reg = <0x550000b0 0x8>;
245 port20x: gpio@550000b8 {
246 compatible = "socionext,uniphier-gpio";
247 reg = <0x550000b8 0x8>;
252 port21x: gpio@550000c0 {
253 compatible = "socionext,uniphier-gpio";
254 reg = <0x550000c0 0x8>;
259 port22x: gpio@550000c8 {
260 compatible = "socionext,uniphier-gpio";
261 reg = <0x550000c8 0x8>;
266 port23x: gpio@550000d0 {
267 compatible = "socionext,uniphier-gpio";
268 reg = <0x550000d0 0x8>;
273 port24x: gpio@550000d8 {
274 compatible = "socionext,uniphier-gpio";
275 reg = <0x550000d8 0x8>;
280 port25x: gpio@550000e0 {
281 compatible = "socionext,uniphier-gpio";
282 reg = <0x550000e0 0x8>;
287 port26x: gpio@550000e8 {
288 compatible = "socionext,uniphier-gpio";
289 reg = <0x550000e8 0x8>;
294 port27x: gpio@550000f0 {
295 compatible = "socionext,uniphier-gpio";
296 reg = <0x550000f0 0x8>;
301 port28x: gpio@550000f8 {
302 compatible = "socionext,uniphier-gpio";
303 reg = <0x550000f8 0x8>;
308 port29x: gpio@55000100 {
309 compatible = "socionext,uniphier-gpio";
310 reg = <0x55000100 0x8>;
315 port30x: gpio@55000108 {
316 compatible = "socionext,uniphier-gpio";
317 reg = <0x55000108 0x8>;
323 compatible = "socionext,uniphier-fi2c";
325 reg = <0x58780000 0x80>;
326 #address-cells = <1>;
328 interrupts = <0 41 4>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_i2c0>;
331 clocks = <&peri_clk 4>;
332 clock-frequency = <100000>;
336 compatible = "socionext,uniphier-fi2c";
338 reg = <0x58781000 0x80>;
339 #address-cells = <1>;
341 interrupts = <0 42 4>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_i2c1>;
344 clocks = <&peri_clk 5>;
345 clock-frequency = <100000>;
349 compatible = "socionext,uniphier-fi2c";
351 reg = <0x58782000 0x80>;
352 #address-cells = <1>;
354 interrupts = <0 43 4>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_i2c2>;
357 clocks = <&peri_clk 6>;
358 clock-frequency = <100000>;
362 compatible = "socionext,uniphier-fi2c";
364 reg = <0x58783000 0x80>;
365 #address-cells = <1>;
367 interrupts = <0 44 4>;
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_i2c3>;
370 clocks = <&peri_clk 7>;
371 clock-frequency = <100000>;
374 /* i2c4 does not exist */
376 /* chip-internal connection for DMD */
378 compatible = "socionext,uniphier-fi2c";
379 reg = <0x58785000 0x80>;
380 #address-cells = <1>;
382 interrupts = <0 25 4>;
383 clocks = <&peri_clk 9>;
384 clock-frequency = <400000>;
387 /* chip-internal connection for HDMI */
389 compatible = "socionext,uniphier-fi2c";
390 reg = <0x58786000 0x80>;
391 #address-cells = <1>;
393 interrupts = <0 26 4>;
394 clocks = <&peri_clk 10>;
395 clock-frequency = <400000>;
398 system_bus: system-bus@58c00000 {
399 compatible = "socionext,uniphier-system-bus";
401 reg = <0x58c00000 0x400>;
402 #address-cells = <2>;
404 pinctrl-names = "default";
405 pinctrl-0 = <&pinctrl_system_bus>;
409 compatible = "socionext,uniphier-smpctrl";
410 reg = <0x59801000 0x400>;
414 compatible = "socionext,uniphier-pro4-mioctrl",
415 "simple-mfd", "syscon";
416 reg = <0x59810000 0x800>;
420 compatible = "socionext,uniphier-pro4-mio-clock";
425 compatible = "socionext,uniphier-pro4-mio-reset";
431 compatible = "socionext,uniphier-pro4-perictrl",
432 "simple-mfd", "syscon";
433 reg = <0x59820000 0x200>;
436 compatible = "socionext,uniphier-pro4-peri-clock";
441 compatible = "socionext,uniphier-pro4-peri-reset";
447 compatible = "socionext,uniphier-sdhc";
449 reg = <0x5a400000 0x200>;
450 interrupts = <0 76 4>;
451 pinctrl-names = "default", "1.8v";
452 pinctrl-0 = <&pinctrl_sd>;
453 pinctrl-1 = <&pinctrl_sd_1v8>;
454 clocks = <&mio_clk 0>;
455 reset-names = "host", "bridge";
456 resets = <&mio_rst 0>, <&mio_rst 3>;
464 emmc: sdhc@5a500000 {
465 compatible = "socionext,uniphier-sdhc";
467 reg = <0x5a500000 0x200>;
468 interrupts = <0 78 4>;
469 pinctrl-names = "default", "1.8v";
470 pinctrl-0 = <&pinctrl_emmc>;
471 pinctrl-1 = <&pinctrl_emmc_1v8>;
472 clocks = <&mio_clk 1>;
473 reset-names = "host", "bridge";
474 resets = <&mio_rst 1>, <&mio_rst 4>;
482 compatible = "socionext,uniphier-sdhc";
484 reg = <0x5a600000 0x200>;
485 interrupts = <0 85 4>;
486 pinctrl-names = "default", "1.8v";
487 pinctrl-0 = <&pinctrl_sd1>;
488 pinctrl-1 = <&pinctrl_sd1_1v8>;
489 clocks = <&mio_clk 2>;
490 resets = <&mio_rst 2>, <&mio_rst 5>;
499 compatible = "socionext,uniphier-ehci", "generic-ehci";
501 reg = <0x5a800100 0x100>;
502 interrupts = <0 80 4>;
503 pinctrl-names = "default";
504 pinctrl-0 = <&pinctrl_usb2>;
505 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
506 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
511 compatible = "socionext,uniphier-ehci", "generic-ehci";
513 reg = <0x5a810100 0x100>;
514 interrupts = <0 81 4>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&pinctrl_usb3>;
517 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
518 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
523 compatible = "socionext,uniphier-pro4-soc-glue",
524 "simple-mfd", "syscon";
525 reg = <0x5f800000 0x2000>;
529 compatible = "socionext,uniphier-pro4-pinctrl";
535 compatible = "simple-mfd", "syscon";
536 reg = <0x5fc20000 0x200>;
540 compatible = "arm,cortex-a9-global-timer";
541 reg = <0x60000200 0x20>;
542 interrupts = <1 11 0x304>;
543 clocks = <&arm_timer_clk>;
547 compatible = "arm,cortex-a9-twd-timer";
548 reg = <0x60000600 0x20>;
549 interrupts = <1 13 0x304>;
550 clocks = <&arm_timer_clk>;
553 intc: interrupt-controller@60001000 {
554 compatible = "arm,cortex-a9-gic";
555 reg = <0x60001000 0x1000>,
557 #interrupt-cells = <3>;
558 interrupt-controller;
562 compatible = "socionext,uniphier-pro4-sysctrl",
563 "simple-mfd", "syscon";
564 reg = <0x61840000 0x10000>;
567 compatible = "socionext,uniphier-pro4-clock";
572 compatible = "socionext,uniphier-pro4-reset";
578 compatible = "socionext,uniphier-pro4-dwc3";
580 reg = <0x65b00000 0x1000>;
581 #address-cells = <1>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_usb0>;
587 compatible = "snps,dwc3";
588 reg = <0x65a00000 0x10000>;
589 interrupts = <0 134 4>;
596 compatible = "socionext,uniphier-pro4-dwc3";
598 reg = <0x65d00000 0x1000>;
599 #address-cells = <1>;
602 pinctrl-names = "default";
603 pinctrl-0 = <&pinctrl_usb1>;
605 compatible = "snps,dwc3";
606 reg = <0x65c00000 0x10000>;
607 interrupts = <0 137 4>;
613 nand: nand@68000000 {
614 compatible = "socionext,uniphier-denali-nand-v5a";
616 reg-names = "nand_data", "denali_reg";
617 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
618 interrupts = <0 65 4>;
619 pinctrl-names = "default";
620 pinctrl-0 = <&pinctrl_nand>;
621 clocks = <&sys_clk 2>;
622 nand-ecc-strength = <8>;
627 /include/ "uniphier-pinctrl.dtsi"