git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-pro4.dtsi

   1 /*
   2  * Device Tree Source for UniPhier Pro4 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 / {
  11         compatible = "socionext,uniphier-pro4";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         enable-method = "psci";
  24                         next-level-cache = <&l2>;
  25                 };
  26
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a9";
  30                         reg = <1>;
  31                         enable-method = "psci";
  32                         next-level-cache = <&l2>;
  33                 };
  34         };
  35
  36         psci {
  37                 compatible = "arm,psci-0.2";
  38                 method = "smc";
  39         };
  40
  41         clocks {
  42                 refclk: ref {
  43                         compatible = "fixed-clock";
  44                         #clock-cells = <0>;
  45                         clock-frequency = <25000000>;
  46                 };
  47
  48                 arm_timer_clk: arm_timer_clk {
  49                         #clock-cells = <0>;
  50                         compatible = "fixed-clock";
  51                         clock-frequency = <50000000>;
  52                 };
  53         };
  54
  55         soc {
  56                 compatible = "simple-bus";
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 ranges;
  60                 interrupt-parent = <&intc>;
  61                 u-boot,dm-pre-reloc;
  62
  63                 l2: l2-cache@500c0000 {
  64                         compatible = "socionext,uniphier-system-cache";
  65                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  66                               <0x506c0000 0x400>;
  67                         interrupts = <0 174 4>, <0 175 4>;
  68                         cache-unified;
  69                         cache-size = <(768 * 1024)>;
  70                         cache-sets = <256>;
  71                         cache-line-size = <128>;
  72                         cache-level = <2>;
  73                 };
  74
  75                 serial0: serial@54006800 {
  76                         compatible = "socionext,uniphier-uart";
  77                         status = "disabled";
  78                         reg = <0x54006800 0x40>;
  79                         interrupts = <0 33 4>;
  80                         pinctrl-names = "default";
  81                         pinctrl-0 = <&pinctrl_uart0>;
  82                         clocks = <&peri_clk 0>;
  83                         clock-frequency = <73728000>;
  84                 };
  85
  86                 serial1: serial@54006900 {
  87                         compatible = "socionext,uniphier-uart";
  88                         status = "disabled";
  89                         reg = <0x54006900 0x40>;
  90                         interrupts = <0 35 4>;
  91                         pinctrl-names = "default";
  92                         pinctrl-0 = <&pinctrl_uart1>;
  93                         clocks = <&peri_clk 1>;
  94                         clock-frequency = <73728000>;
  95                 };
  96
  97                 serial2: serial@54006a00 {
  98                         compatible = "socionext,uniphier-uart";
  99                         status = "disabled";
 100                         reg = <0x54006a00 0x40>;
 101                         interrupts = <0 37 4>;
 102                         pinctrl-names = "default";
 103                         pinctrl-0 = <&pinctrl_uart2>;
 104                         clocks = <&peri_clk 2>;
 105                         clock-frequency = <73728000>;
 106                 };
 107
 108                 serial3: serial@54006b00 {
 109                         compatible = "socionext,uniphier-uart";
 110                         status = "disabled";
 111                         reg = <0x54006b00 0x40>;
 112                         interrupts = <0 177 4>;
 113                         pinctrl-names = "default";
 114                         pinctrl-0 = <&pinctrl_uart3>;
 115                         clocks = <&peri_clk 3>;
 116                         clock-frequency = <73728000>;
 117                 };
 118
 119                 gpio: gpio@55000000 {
 120                         compatible = "socionext,uniphier-gpio";
 121                         reg = <0x55000000 0x200>;
 122                         interrupt-parent = <&aidet>;
 123                         interrupt-controller;
 124                         #interrupt-cells = <2>;
 125                         gpio-controller;
 126                         #gpio-cells = <2>;
 127                         gpio-ranges = <&pinctrl 0 0 0>;
 128                         gpio-ranges-group-names = "gpio_range";
 129                         ngpios = <248>;
 130                 };
 131
 132                 i2c0: i2c@58780000 {
 133                         compatible = "socionext,uniphier-fi2c";
 134                         status = "disabled";
 135                         reg = <0x58780000 0x80>;
 136                         #address-cells = <1>;
 137                         #size-cells = <0>;
 138                         interrupts = <0 41 4>;
 139                         pinctrl-names = "default";
 140                         pinctrl-0 = <&pinctrl_i2c0>;
 141                         clocks = <&peri_clk 4>;
 142                         clock-frequency = <100000>;
 143                 };
 144
 145                 i2c1: i2c@58781000 {
 146                         compatible = "socionext,uniphier-fi2c";
 147                         status = "disabled";
 148                         reg = <0x58781000 0x80>;
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                         interrupts = <0 42 4>;
 152                         pinctrl-names = "default";
 153                         pinctrl-0 = <&pinctrl_i2c1>;
 154                         clocks = <&peri_clk 5>;
 155                         clock-frequency = <100000>;
 156                 };
 157
 158                 i2c2: i2c@58782000 {
 159                         compatible = "socionext,uniphier-fi2c";
 160                         status = "disabled";
 161                         reg = <0x58782000 0x80>;
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164                         interrupts = <0 43 4>;
 165                         pinctrl-names = "default";
 166                         pinctrl-0 = <&pinctrl_i2c2>;
 167                         clocks = <&peri_clk 6>;
 168                         clock-frequency = <100000>;
 169                 };
 170
 171                 i2c3: i2c@58783000 {
 172                         compatible = "socionext,uniphier-fi2c";
 173                         status = "disabled";
 174                         reg = <0x58783000 0x80>;
 175                         #address-cells = <1>;
 176                         #size-cells = <0>;
 177                         interrupts = <0 44 4>;
 178                         pinctrl-names = "default";
 179                         pinctrl-0 = <&pinctrl_i2c3>;
 180                         clocks = <&peri_clk 7>;
 181                         clock-frequency = <100000>;
 182                 };
 183
 184                 /* i2c4 does not exist */
 185
 186                 /* chip-internal connection for DMD */
 187                 i2c5: i2c@58785000 {
 188                         compatible = "socionext,uniphier-fi2c";
 189                         reg = <0x58785000 0x80>;
 190                         #address-cells = <1>;
 191                         #size-cells = <0>;
 192                         interrupts = <0 25 4>;
 193                         clocks = <&peri_clk 9>;
 194                         clock-frequency = <400000>;
 195                 };
 196
 197                 /* chip-internal connection for HDMI */
 198                 i2c6: i2c@58786000 {
 199                         compatible = "socionext,uniphier-fi2c";
 200                         reg = <0x58786000 0x80>;
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                         interrupts = <0 26 4>;
 204                         clocks = <&peri_clk 10>;
 205                         clock-frequency = <400000>;
 206                 };
 207
 208                 system_bus: system-bus@58c00000 {
 209                         compatible = "socionext,uniphier-system-bus";
 210                         status = "disabled";
 211                         reg = <0x58c00000 0x400>;
 212                         #address-cells = <2>;
 213                         #size-cells = <1>;
 214                         pinctrl-names = "default";
 215                         pinctrl-0 = <&pinctrl_system_bus>;
 216                 };
 217
 218                 smpctrl@59801000 {
 219                         compatible = "socionext,uniphier-smpctrl";
 220                         reg = <0x59801000 0x400>;
 221                 };
 222
 223                 mioctrl@59810000 {
 224                         compatible = "socionext,uniphier-pro4-mioctrl",
 225                                      "simple-mfd", "syscon";
 226                         reg = <0x59810000 0x800>;
 227                         u-boot,dm-pre-reloc;
 228
 229                         mio_clk: clock {
 230                                 compatible = "socionext,uniphier-pro4-mio-clock";
 231                                 #clock-cells = <1>;
 232                         };
 233
 234                         mio_rst: reset {
 235                                 compatible = "socionext,uniphier-pro4-mio-reset";
 236                                 #reset-cells = <1>;
 237                         };
 238                 };
 239
 240                 perictrl@59820000 {
 241                         compatible = "socionext,uniphier-pro4-perictrl",
 242                                      "simple-mfd", "syscon";
 243                         reg = <0x59820000 0x200>;
 244
 245                         peri_clk: clock {
 246                                 compatible = "socionext,uniphier-pro4-peri-clock";
 247                                 #clock-cells = <1>;
 248                         };
 249
 250                         peri_rst: reset {
 251                                 compatible = "socionext,uniphier-pro4-peri-reset";
 252                                 #reset-cells = <1>;
 253                         };
 254                 };
 255
 256                 sd: sdhc@5a400000 {
 257                         compatible = "socionext,uniphier-sdhc";
 258                         status = "disabled";
 259                         reg = <0x5a400000 0x200>;
 260                         interrupts = <0 76 4>;
 261                         pinctrl-names = "default", "1.8v";
 262                         pinctrl-0 = <&pinctrl_sd>;
 263                         pinctrl-1 = <&pinctrl_sd_1v8>;
 264                         clocks = <&mio_clk 0>;
 265                         reset-names = "host", "bridge";
 266                         resets = <&mio_rst 0>, <&mio_rst 3>;
 267                         bus-width = <4>;
 268                         cap-sd-highspeed;
 269                         sd-uhs-sdr12;
 270                         sd-uhs-sdr25;
 271                         sd-uhs-sdr50;
 272                 };
 273
 274                 emmc: sdhc@5a500000 {
 275                         compatible = "socionext,uniphier-sdhc";
 276                         status = "disabled";
 277                         reg = <0x5a500000 0x200>;
 278                         interrupts = <0 78 4>;
 279                         pinctrl-names = "default", "1.8v";
 280                         pinctrl-0 = <&pinctrl_emmc>;
 281                         pinctrl-1 = <&pinctrl_emmc_1v8>;
 282                         clocks = <&mio_clk 1>;
 283                         reset-names = "host", "bridge";
 284                         resets = <&mio_rst 1>, <&mio_rst 4>;
 285                         bus-width = <8>;
 286                         non-removable;
 287                         cap-mmc-highspeed;
 288                         cap-mmc-hw-reset;
 289                 };
 290
 291                 sd1: sdhc@5a600000 {
 292                         compatible = "socionext,uniphier-sdhc";
 293                         status = "disabled";
 294                         reg = <0x5a600000 0x200>;
 295                         interrupts = <0 85 4>;
 296                         pinctrl-names = "default", "1.8v";
 297                         pinctrl-0 = <&pinctrl_sd1>;
 298                         pinctrl-1 = <&pinctrl_sd1_1v8>;
 299                         clocks = <&mio_clk 2>;
 300                         resets = <&mio_rst 2>, <&mio_rst 5>;
 301                         bus-width = <4>;
 302                         cap-sd-highspeed;
 303                         sd-uhs-sdr12;
 304                         sd-uhs-sdr25;
 305                         sd-uhs-sdr50;
 306                 };
 307
 308                 usb2: usb@5a800100 {
 309                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 310                         status = "disabled";
 311                         reg = <0x5a800100 0x100>;
 312                         interrupts = <0 80 4>;
 313                         pinctrl-names = "default";
 314                         pinctrl-0 = <&pinctrl_usb2>;
 315                         clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
 316                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 317                                  <&mio_rst 12>;
 318                 };
 319
 320                 usb3: usb@5a810100 {
 321                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 322                         status = "disabled";
 323                         reg = <0x5a810100 0x100>;
 324                         interrupts = <0 81 4>;
 325                         pinctrl-names = "default";
 326                         pinctrl-0 = <&pinctrl_usb3>;
 327                         clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
 328                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 329                                  <&mio_rst 13>;
 330                 };
 331
 332                 soc-glue@5f800000 {
 333                         compatible = "socionext,uniphier-pro4-soc-glue",
 334                                      "simple-mfd", "syscon";
 335                         reg = <0x5f800000 0x2000>;
 336                         u-boot,dm-pre-reloc;
 337
 338                         pinctrl: pinctrl {
 339                                 compatible = "socionext,uniphier-pro4-pinctrl";
 340                                 u-boot,dm-pre-reloc;
 341                         };
 342                 };
 343
 344                 aidet: aidet@5fc20000 {
 345                         compatible = "socionext,uniphier-pro4-aidet";
 346                         reg = <0x5fc20000 0x200>;
 347                         interrupt-controller;
 348                         #interrupt-cells = <2>;
 349                 };
 350
 351                 timer@60000200 {
 352                         compatible = "arm,cortex-a9-global-timer";
 353                         reg = <0x60000200 0x20>;
 354                         interrupts = <1 11 0x304>;
 355                         clocks = <&arm_timer_clk>;
 356                 };
 357
 358                 timer@60000600 {
 359                         compatible = "arm,cortex-a9-twd-timer";
 360                         reg = <0x60000600 0x20>;
 361                         interrupts = <1 13 0x304>;
 362                         clocks = <&arm_timer_clk>;
 363                 };
 364
 365                 intc: interrupt-controller@60001000 {
 366                         compatible = "arm,cortex-a9-gic";
 367                         reg = <0x60001000 0x1000>,
 368                               <0x60000100 0x100>;
 369                         #interrupt-cells = <3>;
 370                         interrupt-controller;
 371                 };
 372
 373                 sysctrl@61840000 {
 374                         compatible = "socionext,uniphier-pro4-sysctrl",
 375                                      "simple-mfd", "syscon";
 376                         reg = <0x61840000 0x10000>;
 377
 378                         sys_clk: clock {
 379                                 compatible = "socionext,uniphier-pro4-clock";
 380                                 #clock-cells = <1>;
 381                         };
 382
 383                         sys_rst: reset {
 384                                 compatible = "socionext,uniphier-pro4-reset";
 385                                 #reset-cells = <1>;
 386                         };
 387                 };
 388
 389                 usb0: usb@65b00000 {
 390                         compatible = "socionext,uniphier-pro4-dwc3";
 391                         status = "disabled";
 392                         reg = <0x65b00000 0x1000>;
 393                         #address-cells = <1>;
 394                         #size-cells = <1>;
 395                         ranges;
 396                         pinctrl-names = "default";
 397                         pinctrl-0 = <&pinctrl_usb0>;
 398                         dwc3@65a00000 {
 399                                 compatible = "snps,dwc3";
 400                                 reg = <0x65a00000 0x10000>;
 401                                 interrupts = <0 134 4>;
 402                                 dr_mode = "host";
 403                                 tx-fifo-resize;
 404                         };
 405                 };
 406
 407                 usb1: usb@65d00000 {
 408                         compatible = "socionext,uniphier-pro4-dwc3";
 409                         status = "disabled";
 410                         reg = <0x65d00000 0x1000>;
 411                         #address-cells = <1>;
 412                         #size-cells = <1>;
 413                         ranges;
 414                         pinctrl-names = "default";
 415                         pinctrl-0 = <&pinctrl_usb1>;
 416                         dwc3@65c00000 {
 417                                 compatible = "snps,dwc3";
 418                                 reg = <0x65c00000 0x10000>;
 419                                 interrupts = <0 137 4>;
 420                                 dr_mode = "host";
 421                                 tx-fifo-resize;
 422                         };
 423                 };
 424
 425                 nand: nand@68000000 {
 426                         compatible = "socionext,uniphier-denali-nand-v5a";
 427                         status = "disabled";
 428                         reg-names = "nand_data", "denali_reg";
 429                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 430                         interrupts = <0 65 4>;
 431                         pinctrl-names = "default";
 432                         pinctrl-0 = <&pinctrl_nand>;
 433                         clocks = <&sys_clk 2>;
 434                 };
 435         };
 436 };
 437
 438 #include "uniphier-pinctrl.dtsi"