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[u-boot] / arch / arm / dts / uniphier-pro4.dtsi
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Device Tree Source for UniPhier Pro4 SoC
4 //
5 // Copyright (C) 2015-2016 Socionext Inc.
6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9
10 / {
11         compatible = "socionext,uniphier-pro4";
12         #address-cells = <1>;
13         #size-cells = <1>;
14
15         cpus {
16                 #address-cells = <1>;
17                 #size-cells = <0>;
18
19                 cpu@0 {
20                         device_type = "cpu";
21                         compatible = "arm,cortex-a9";
22                         reg = <0>;
23                         enable-method = "psci";
24                         next-level-cache = <&l2>;
25                 };
26
27                 cpu@1 {
28                         device_type = "cpu";
29                         compatible = "arm,cortex-a9";
30                         reg = <1>;
31                         enable-method = "psci";
32                         next-level-cache = <&l2>;
33                 };
34         };
35
36         psci {
37                 compatible = "arm,psci-0.2";
38                 method = "smc";
39         };
40
41         clocks {
42                 refclk: ref {
43                         compatible = "fixed-clock";
44                         #clock-cells = <0>;
45                         clock-frequency = <25000000>;
46                 };
47
48                 arm_timer_clk: arm-timer {
49                         #clock-cells = <0>;
50                         compatible = "fixed-clock";
51                         clock-frequency = <50000000>;
52                 };
53         };
54
55         soc {
56                 compatible = "simple-bus";
57                 #address-cells = <1>;
58                 #size-cells = <1>;
59                 ranges;
60                 interrupt-parent = <&intc>;
61
62                 l2: l2-cache@500c0000 {
63                         compatible = "socionext,uniphier-system-cache";
64                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
65                               <0x506c0000 0x400>;
66                         interrupts = <0 174 4>, <0 175 4>;
67                         cache-unified;
68                         cache-size = <(768 * 1024)>;
69                         cache-sets = <256>;
70                         cache-line-size = <128>;
71                         cache-level = <2>;
72                 };
73
74                 serial0: serial@54006800 {
75                         compatible = "socionext,uniphier-uart";
76                         status = "disabled";
77                         reg = <0x54006800 0x40>;
78                         interrupts = <0 33 4>;
79                         pinctrl-names = "default";
80                         pinctrl-0 = <&pinctrl_uart0>;
81                         clocks = <&peri_clk 0>;
82                         clock-frequency = <73728000>;
83                         resets = <&peri_rst 0>;
84                 };
85
86                 serial1: serial@54006900 {
87                         compatible = "socionext,uniphier-uart";
88                         status = "disabled";
89                         reg = <0x54006900 0x40>;
90                         interrupts = <0 35 4>;
91                         pinctrl-names = "default";
92                         pinctrl-0 = <&pinctrl_uart1>;
93                         clocks = <&peri_clk 1>;
94                         clock-frequency = <73728000>;
95                         resets = <&peri_rst 1>;
96                 };
97
98                 serial2: serial@54006a00 {
99                         compatible = "socionext,uniphier-uart";
100                         status = "disabled";
101                         reg = <0x54006a00 0x40>;
102                         interrupts = <0 37 4>;
103                         pinctrl-names = "default";
104                         pinctrl-0 = <&pinctrl_uart2>;
105                         clocks = <&peri_clk 2>;
106                         clock-frequency = <73728000>;
107                         resets = <&peri_rst 2>;
108                 };
109
110                 serial3: serial@54006b00 {
111                         compatible = "socionext,uniphier-uart";
112                         status = "disabled";
113                         reg = <0x54006b00 0x40>;
114                         interrupts = <0 177 4>;
115                         pinctrl-names = "default";
116                         pinctrl-0 = <&pinctrl_uart3>;
117                         clocks = <&peri_clk 3>;
118                         clock-frequency = <73728000>;
119                         resets = <&peri_rst 3>;
120                 };
121
122                 gpio: gpio@55000000 {
123                         compatible = "socionext,uniphier-gpio";
124                         reg = <0x55000000 0x200>;
125                         interrupt-parent = <&aidet>;
126                         interrupt-controller;
127                         #interrupt-cells = <2>;
128                         gpio-controller;
129                         #gpio-cells = <2>;
130                         gpio-ranges = <&pinctrl 0 0 0>;
131                         gpio-ranges-group-names = "gpio_range";
132                         ngpios = <248>;
133                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
134                 };
135
136                 i2c0: i2c@58780000 {
137                         compatible = "socionext,uniphier-fi2c";
138                         status = "disabled";
139                         reg = <0x58780000 0x80>;
140                         #address-cells = <1>;
141                         #size-cells = <0>;
142                         interrupts = <0 41 4>;
143                         pinctrl-names = "default";
144                         pinctrl-0 = <&pinctrl_i2c0>;
145                         clocks = <&peri_clk 4>;
146                         resets = <&peri_rst 4>;
147                         clock-frequency = <100000>;
148                 };
149
150                 i2c1: i2c@58781000 {
151                         compatible = "socionext,uniphier-fi2c";
152                         status = "disabled";
153                         reg = <0x58781000 0x80>;
154                         #address-cells = <1>;
155                         #size-cells = <0>;
156                         interrupts = <0 42 4>;
157                         pinctrl-names = "default";
158                         pinctrl-0 = <&pinctrl_i2c1>;
159                         clocks = <&peri_clk 5>;
160                         resets = <&peri_rst 5>;
161                         clock-frequency = <100000>;
162                 };
163
164                 i2c2: i2c@58782000 {
165                         compatible = "socionext,uniphier-fi2c";
166                         status = "disabled";
167                         reg = <0x58782000 0x80>;
168                         #address-cells = <1>;
169                         #size-cells = <0>;
170                         interrupts = <0 43 4>;
171                         pinctrl-names = "default";
172                         pinctrl-0 = <&pinctrl_i2c2>;
173                         clocks = <&peri_clk 6>;
174                         resets = <&peri_rst 6>;
175                         clock-frequency = <100000>;
176                 };
177
178                 i2c3: i2c@58783000 {
179                         compatible = "socionext,uniphier-fi2c";
180                         status = "disabled";
181                         reg = <0x58783000 0x80>;
182                         #address-cells = <1>;
183                         #size-cells = <0>;
184                         interrupts = <0 44 4>;
185                         pinctrl-names = "default";
186                         pinctrl-0 = <&pinctrl_i2c3>;
187                         clocks = <&peri_clk 7>;
188                         resets = <&peri_rst 7>;
189                         clock-frequency = <100000>;
190                 };
191
192                 /* i2c4 does not exist */
193
194                 /* chip-internal connection for DMD */
195                 i2c5: i2c@58785000 {
196                         compatible = "socionext,uniphier-fi2c";
197                         reg = <0x58785000 0x80>;
198                         #address-cells = <1>;
199                         #size-cells = <0>;
200                         interrupts = <0 25 4>;
201                         clocks = <&peri_clk 9>;
202                         resets = <&peri_rst 9>;
203                         clock-frequency = <400000>;
204                 };
205
206                 /* chip-internal connection for HDMI */
207                 i2c6: i2c@58786000 {
208                         compatible = "socionext,uniphier-fi2c";
209                         reg = <0x58786000 0x80>;
210                         #address-cells = <1>;
211                         #size-cells = <0>;
212                         interrupts = <0 26 4>;
213                         clocks = <&peri_clk 10>;
214                         resets = <&peri_rst 10>;
215                         clock-frequency = <400000>;
216                 };
217
218                 system_bus: system-bus@58c00000 {
219                         compatible = "socionext,uniphier-system-bus";
220                         status = "disabled";
221                         reg = <0x58c00000 0x400>;
222                         #address-cells = <2>;
223                         #size-cells = <1>;
224                         pinctrl-names = "default";
225                         pinctrl-0 = <&pinctrl_system_bus>;
226                 };
227
228                 smpctrl@59801000 {
229                         compatible = "socionext,uniphier-smpctrl";
230                         reg = <0x59801000 0x400>;
231                 };
232
233                 mioctrl@59810000 {
234                         compatible = "socionext,uniphier-pro4-mioctrl",
235                                      "simple-mfd", "syscon";
236                         reg = <0x59810000 0x800>;
237
238                         mio_clk: clock {
239                                 compatible = "socionext,uniphier-pro4-mio-clock";
240                                 #clock-cells = <1>;
241                         };
242
243                         mio_rst: reset {
244                                 compatible = "socionext,uniphier-pro4-mio-reset";
245                                 #reset-cells = <1>;
246                         };
247                 };
248
249                 perictrl@59820000 {
250                         compatible = "socionext,uniphier-pro4-perictrl",
251                                      "simple-mfd", "syscon";
252                         reg = <0x59820000 0x200>;
253
254                         peri_clk: clock {
255                                 compatible = "socionext,uniphier-pro4-peri-clock";
256                                 #clock-cells = <1>;
257                         };
258
259                         peri_rst: reset {
260                                 compatible = "socionext,uniphier-pro4-peri-reset";
261                                 #reset-cells = <1>;
262                         };
263                 };
264
265                 sd: sdhc@5a400000 {
266                         compatible = "socionext,uniphier-sdhc";
267                         status = "disabled";
268                         reg = <0x5a400000 0x200>;
269                         interrupts = <0 76 4>;
270                         pinctrl-names = "default", "1.8v";
271                         pinctrl-0 = <&pinctrl_sd>;
272                         pinctrl-1 = <&pinctrl_sd_1v8>;
273                         clocks = <&mio_clk 0>;
274                         reset-names = "host", "bridge";
275                         resets = <&mio_rst 0>, <&mio_rst 3>;
276                         bus-width = <4>;
277                         cap-sd-highspeed;
278                         sd-uhs-sdr12;
279                         sd-uhs-sdr25;
280                         sd-uhs-sdr50;
281                 };
282
283                 emmc: sdhc@5a500000 {
284                         compatible = "socionext,uniphier-sdhc";
285                         status = "disabled";
286                         reg = <0x5a500000 0x200>;
287                         interrupts = <0 78 4>;
288                         pinctrl-names = "default", "1.8v";
289                         pinctrl-0 = <&pinctrl_emmc>;
290                         pinctrl-1 = <&pinctrl_emmc_1v8>;
291                         clocks = <&mio_clk 1>;
292                         reset-names = "host", "bridge";
293                         resets = <&mio_rst 1>, <&mio_rst 4>;
294                         bus-width = <8>;
295                         non-removable;
296                         cap-mmc-highspeed;
297                         cap-mmc-hw-reset;
298                 };
299
300                 sd1: sdhc@5a600000 {
301                         compatible = "socionext,uniphier-sdhc";
302                         status = "disabled";
303                         reg = <0x5a600000 0x200>;
304                         interrupts = <0 85 4>;
305                         pinctrl-names = "default", "1.8v";
306                         pinctrl-0 = <&pinctrl_sd1>;
307                         pinctrl-1 = <&pinctrl_sd1_1v8>;
308                         clocks = <&mio_clk 2>;
309                         resets = <&mio_rst 2>, <&mio_rst 5>;
310                         bus-width = <4>;
311                         cap-sd-highspeed;
312                         sd-uhs-sdr12;
313                         sd-uhs-sdr25;
314                         sd-uhs-sdr50;
315                 };
316
317                 usb2: usb@5a800100 {
318                         compatible = "socionext,uniphier-ehci", "generic-ehci";
319                         status = "disabled";
320                         reg = <0x5a800100 0x100>;
321                         interrupts = <0 80 4>;
322                         pinctrl-names = "default";
323                         pinctrl-0 = <&pinctrl_usb2>;
324                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
325                                  <&mio_clk 12>;
326                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
327                                  <&mio_rst 12>;
328                         has-transaction-translator;
329                 };
330
331                 usb3: usb@5a810100 {
332                         compatible = "socionext,uniphier-ehci", "generic-ehci";
333                         status = "disabled";
334                         reg = <0x5a810100 0x100>;
335                         interrupts = <0 81 4>;
336                         pinctrl-names = "default";
337                         pinctrl-0 = <&pinctrl_usb3>;
338                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
339                                  <&mio_clk 13>;
340                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
341                                  <&mio_rst 13>;
342                         has-transaction-translator;
343                 };
344
345                 soc_glue: soc-glue@5f800000 {
346                         compatible = "socionext,uniphier-pro4-soc-glue",
347                                      "simple-mfd", "syscon";
348                         reg = <0x5f800000 0x2000>;
349
350                         pinctrl: pinctrl {
351                                 compatible = "socionext,uniphier-pro4-pinctrl";
352                         };
353                 };
354
355                 soc-glue@5f900000 {
356                         compatible = "socionext,uniphier-pro4-soc-glue-debug",
357                                      "simple-mfd";
358                         #address-cells = <1>;
359                         #size-cells = <1>;
360                         ranges = <0 0x5f900000 0x2000>;
361
362                         efuse@100 {
363                                 compatible = "socionext,uniphier-efuse";
364                                 reg = <0x100 0x28>;
365                         };
366
367                         efuse@130 {
368                                 compatible = "socionext,uniphier-efuse";
369                                 reg = <0x130 0x8>;
370                         };
371
372                         efuse@200 {
373                                 compatible = "socionext,uniphier-efuse";
374                                 reg = <0x200 0x14>;
375                         };
376                 };
377
378                 aidet: aidet@5fc20000 {
379                         compatible = "socionext,uniphier-pro4-aidet";
380                         reg = <0x5fc20000 0x200>;
381                         interrupt-controller;
382                         #interrupt-cells = <2>;
383                 };
384
385                 timer@60000200 {
386                         compatible = "arm,cortex-a9-global-timer";
387                         reg = <0x60000200 0x20>;
388                         interrupts = <1 11 0x304>;
389                         clocks = <&arm_timer_clk>;
390                 };
391
392                 timer@60000600 {
393                         compatible = "arm,cortex-a9-twd-timer";
394                         reg = <0x60000600 0x20>;
395                         interrupts = <1 13 0x304>;
396                         clocks = <&arm_timer_clk>;
397                 };
398
399                 intc: interrupt-controller@60001000 {
400                         compatible = "arm,cortex-a9-gic";
401                         reg = <0x60001000 0x1000>,
402                               <0x60000100 0x100>;
403                         #interrupt-cells = <3>;
404                         interrupt-controller;
405                 };
406
407                 sysctrl@61840000 {
408                         compatible = "socionext,uniphier-pro4-sysctrl",
409                                      "simple-mfd", "syscon";
410                         reg = <0x61840000 0x10000>;
411
412                         sys_clk: clock {
413                                 compatible = "socionext,uniphier-pro4-clock";
414                                 #clock-cells = <1>;
415                         };
416
417                         sys_rst: reset {
418                                 compatible = "socionext,uniphier-pro4-reset";
419                                 #reset-cells = <1>;
420                         };
421                 };
422
423                 eth: ethernet@65000000 {
424                         compatible = "socionext,uniphier-pro4-ave4";
425                         status = "disabled";
426                         reg = <0x65000000 0x8500>;
427                         interrupts = <0 66 4>;
428                         pinctrl-names = "default";
429                         pinctrl-0 = <&pinctrl_ether_rgmii>;
430                         clock-names = "gio", "ether", "ether-gb", "ether-phy";
431                         clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>,
432                                 <&sys_clk 10>;
433                         reset-names = "gio", "ether";
434                         resets = <&sys_rst 12>, <&sys_rst 6>;
435                         phy-mode = "rgmii";
436                         local-mac-address = [00 00 00 00 00 00];
437                         socionext,syscon-phy-mode = <&soc_glue 0>;
438
439                         mdio: mdio {
440                                 #address-cells = <1>;
441                                 #size-cells = <0>;
442                         };
443                 };
444
445                 usb0: usb@65b00000 {
446                         compatible = "socionext,uniphier-pro4-dwc3";
447                         status = "disabled";
448                         reg = <0x65b00000 0x1000>;
449                         #address-cells = <1>;
450                         #size-cells = <1>;
451                         ranges;
452                         pinctrl-names = "default";
453                         pinctrl-0 = <&pinctrl_usb0>;
454                         dwc3@65a00000 {
455                                 compatible = "snps,dwc3";
456                                 reg = <0x65a00000 0x10000>;
457                                 interrupts = <0 134 4>;
458                                 dr_mode = "host";
459                                 tx-fifo-resize;
460                         };
461                 };
462
463                 usb1: usb@65d00000 {
464                         compatible = "socionext,uniphier-pro4-dwc3";
465                         status = "disabled";
466                         reg = <0x65d00000 0x1000>;
467                         #address-cells = <1>;
468                         #size-cells = <1>;
469                         ranges;
470                         pinctrl-names = "default";
471                         pinctrl-0 = <&pinctrl_usb1>;
472                         dwc3@65c00000 {
473                                 compatible = "snps,dwc3";
474                                 reg = <0x65c00000 0x10000>;
475                                 interrupts = <0 137 4>;
476                                 dr_mode = "host";
477                                 tx-fifo-resize;
478                         };
479                 };
480
481                 nand: nand@68000000 {
482                         compatible = "socionext,uniphier-denali-nand-v5a";
483                         status = "disabled";
484                         reg-names = "nand_data", "denali_reg";
485                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
486                         interrupts = <0 65 4>;
487                         pinctrl-names = "default";
488                         pinctrl-0 = <&pinctrl_nand>;
489                         clocks = <&sys_clk 2>;
490                         resets = <&sys_rst 2>;
491                 };
492         };
493 };
494
495 #include "uniphier-pinctrl.dtsi"