2 * Device Tree Source for UniPhier Pro4 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: GPL-2.0+ X11
10 /include/ "uniphier-common32.dtsi"
13 compatible = "socionext,uniphier-pro4";
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
29 compatible = "arm,cortex-a9";
31 enable-method = "psci";
32 next-level-cache = <&l2>;
37 arm_timer_clk: arm_timer_clk {
39 compatible = "fixed-clock";
40 clock-frequency = <50000000>;
45 compatible = "fixed-clock";
46 clock-frequency = <73728000>;
51 compatible = "fixed-clock";
52 clock-frequency = <50000000>;
58 l2: l2-cache@500c0000 {
59 compatible = "socionext,uniphier-system-cache";
60 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
61 interrupts = <0 174 4>, <0 175 4>;
63 cache-size = <(768 * 1024)>;
65 cache-line-size = <128>;
69 port0x: gpio@55000008 {
70 compatible = "socionext,uniphier-gpio";
71 reg = <0x55000008 0x8>;
76 port1x: gpio@55000010 {
77 compatible = "socionext,uniphier-gpio";
78 reg = <0x55000010 0x8>;
83 port2x: gpio@55000018 {
84 compatible = "socionext,uniphier-gpio";
85 reg = <0x55000018 0x8>;
90 port3x: gpio@55000020 {
91 compatible = "socionext,uniphier-gpio";
92 reg = <0x55000020 0x8>;
97 port4: gpio@55000028 {
98 compatible = "socionext,uniphier-gpio";
99 reg = <0x55000028 0x8>;
104 port5x: gpio@55000030 {
105 compatible = "socionext,uniphier-gpio";
106 reg = <0x55000030 0x8>;
111 port6x: gpio@55000038 {
112 compatible = "socionext,uniphier-gpio";
113 reg = <0x55000038 0x8>;
118 port7x: gpio@55000040 {
119 compatible = "socionext,uniphier-gpio";
120 reg = <0x55000040 0x8>;
125 port8x: gpio@55000048 {
126 compatible = "socionext,uniphier-gpio";
127 reg = <0x55000048 0x8>;
132 port9x: gpio@55000050 {
133 compatible = "socionext,uniphier-gpio";
134 reg = <0x55000050 0x8>;
139 port10x: gpio@55000058 {
140 compatible = "socionext,uniphier-gpio";
141 reg = <0x55000058 0x8>;
146 port11x: gpio@55000060 {
147 compatible = "socionext,uniphier-gpio";
148 reg = <0x55000060 0x8>;
153 port12x: gpio@55000068 {
154 compatible = "socionext,uniphier-gpio";
155 reg = <0x55000068 0x8>;
160 port13x: gpio@55000070 {
161 compatible = "socionext,uniphier-gpio";
162 reg = <0x55000070 0x8>;
167 port14x: gpio@55000078 {
168 compatible = "socionext,uniphier-gpio";
169 reg = <0x55000078 0x8>;
174 port17x: gpio@550000a0 {
175 compatible = "socionext,uniphier-gpio";
176 reg = <0x550000a0 0x8>;
181 port18x: gpio@550000a8 {
182 compatible = "socionext,uniphier-gpio";
183 reg = <0x550000a8 0x8>;
188 port19x: gpio@550000b0 {
189 compatible = "socionext,uniphier-gpio";
190 reg = <0x550000b0 0x8>;
195 port20x: gpio@550000b8 {
196 compatible = "socionext,uniphier-gpio";
197 reg = <0x550000b8 0x8>;
202 port21x: gpio@550000c0 {
203 compatible = "socionext,uniphier-gpio";
204 reg = <0x550000c0 0x8>;
209 port22x: gpio@550000c8 {
210 compatible = "socionext,uniphier-gpio";
211 reg = <0x550000c8 0x8>;
216 port23x: gpio@550000d0 {
217 compatible = "socionext,uniphier-gpio";
218 reg = <0x550000d0 0x8>;
223 port24x: gpio@550000d8 {
224 compatible = "socionext,uniphier-gpio";
225 reg = <0x550000d8 0x8>;
230 port25x: gpio@550000e0 {
231 compatible = "socionext,uniphier-gpio";
232 reg = <0x550000e0 0x8>;
237 port26x: gpio@550000e8 {
238 compatible = "socionext,uniphier-gpio";
239 reg = <0x550000e8 0x8>;
244 port27x: gpio@550000f0 {
245 compatible = "socionext,uniphier-gpio";
246 reg = <0x550000f0 0x8>;
251 port28x: gpio@550000f8 {
252 compatible = "socionext,uniphier-gpio";
253 reg = <0x550000f8 0x8>;
258 port29x: gpio@55000100 {
259 compatible = "socionext,uniphier-gpio";
260 reg = <0x55000100 0x8>;
265 port30x: gpio@55000108 {
266 compatible = "socionext,uniphier-gpio";
267 reg = <0x55000108 0x8>;
273 compatible = "socionext,uniphier-fi2c";
275 reg = <0x58780000 0x80>;
276 #address-cells = <1>;
278 interrupts = <0 41 4>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_i2c0>;
282 clock-frequency = <100000>;
286 compatible = "socionext,uniphier-fi2c";
288 reg = <0x58781000 0x80>;
289 #address-cells = <1>;
291 interrupts = <0 42 4>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_i2c1>;
295 clock-frequency = <100000>;
299 compatible = "socionext,uniphier-fi2c";
301 reg = <0x58782000 0x80>;
302 #address-cells = <1>;
304 interrupts = <0 43 4>;
305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_i2c2>;
308 clock-frequency = <100000>;
312 compatible = "socionext,uniphier-fi2c";
314 reg = <0x58783000 0x80>;
315 #address-cells = <1>;
317 interrupts = <0 44 4>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_i2c3>;
321 clock-frequency = <100000>;
324 /* i2c4 does not exist */
326 /* chip-internal connection for DMD */
328 compatible = "socionext,uniphier-fi2c";
329 reg = <0x58785000 0x80>;
330 #address-cells = <1>;
332 interrupts = <0 25 4>;
334 clock-frequency = <400000>;
337 /* chip-internal connection for HDMI */
339 compatible = "socionext,uniphier-fi2c";
340 reg = <0x58786000 0x80>;
341 #address-cells = <1>;
343 interrupts = <0 26 4>;
345 clock-frequency = <400000>;
349 compatible = "socionext,uniphier-sdhc";
351 reg = <0x5a400000 0x200>;
352 interrupts = <0 76 4>;
353 pinctrl-names = "default", "1.8v";
354 pinctrl-0 = <&pinctrl_sd>;
355 pinctrl-1 = <&pinctrl_sd_1v8>;
356 clocks = <&mio_clk 0>;
357 reset-names = "host", "bridge";
358 resets = <&mio_rst 0>, <&mio_rst 3>;
362 emmc: sdhc@5a500000 {
363 compatible = "socionext,uniphier-sdhc";
365 reg = <0x5a500000 0x200>;
366 interrupts = <0 78 4>;
367 pinctrl-names = "default", "1.8v";
368 pinctrl-0 = <&pinctrl_emmc>;
369 pinctrl-1 = <&pinctrl_emmc_1v8>;
370 clocks = <&mio_clk 1>;
371 reset-names = "host", "bridge", "hw-reset";
372 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
378 compatible = "socionext,uniphier-sdhc";
380 reg = <0x5a600000 0x200>;
381 interrupts = <0 85 4>;
382 pinctrl-names = "default", "1.8v";
383 pinctrl-0 = <&pinctrl_sd1>;
384 pinctrl-1 = <&pinctrl_sd1_1v8>;
385 clocks = <&mio_clk 2>;
386 resets = <&mio_rst 2>, <&mio_rst 5>;
391 compatible = "socionext,uniphier-ehci", "generic-ehci";
393 reg = <0x5a800100 0x100>;
394 interrupts = <0 80 4>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_usb2>;
397 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
398 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
403 compatible = "socionext,uniphier-ehci", "generic-ehci";
405 reg = <0x5a810100 0x100>;
406 interrupts = <0 81 4>;
407 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_usb3>;
409 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
410 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
415 compatible = "simple-mfd", "syscon";
416 reg = <0x5fc20000 0x200>;
420 compatible = "socionext,uniphier-xhci", "generic-xhci";
422 reg = <0x65a00000 0x100>;
423 interrupts = <0 134 4>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_usb0>;
429 compatible = "socionext,uniphier-xhci", "generic-xhci";
431 reg = <0x65c00000 0x100>;
432 interrupts = <0 137 4>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_usb1>;
439 clock-frequency = <25000000>;
443 clock-frequency = <73728000>;
447 clock-frequency = <73728000>;
451 clock-frequency = <73728000>;
455 clock-frequency = <73728000>;
459 compatible = "socionext,uniphier-pro4-mio-clock";
463 compatible = "socionext,uniphier-pro4-mio-reset";
467 compatible = "socionext,uniphier-pro4-peri-clock";
471 compatible = "socionext,uniphier-pro4-peri-reset";
475 compatible = "socionext,uniphier-pro4-pinctrl";
479 compatible = "socionext,uniphier-pro4-clock";
483 compatible = "socionext,uniphier-pro4-reset";