git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-pro4.dtsi

   1 /*
   2  * Device Tree Source for UniPhier Pro4 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+        X11
   8  */
   9
  10 /include/ "uniphier-common32.dtsi"
  11
  12 / {
  13         compatible = "socionext,uniphier-pro4";
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         enable-method = "psci";
  24                         next-level-cache = <&l2>;
  25                 };
  26
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a9";
  30                         reg = <1>;
  31                         enable-method = "psci";
  32                         next-level-cache = <&l2>;
  33                 };
  34         };
  35
  36         clocks {
  37                 arm_timer_clk: arm_timer_clk {
  38                         #clock-cells = <0>;
  39                         compatible = "fixed-clock";
  40                         clock-frequency = <50000000>;
  41                 };
  42
  43                 uart_clk: uart_clk {
  44                         #clock-cells = <0>;
  45                         compatible = "fixed-clock";
  46                         clock-frequency = <73728000>;
  47                 };
  48
  49                 i2c_clk: i2c_clk {
  50                         #clock-cells = <0>;
  51                         compatible = "fixed-clock";
  52                         clock-frequency = <50000000>;
  53                 };
  54         };
  55 };
  56
  57 &soc {
  58         l2: l2-cache@500c0000 {
  59                 compatible = "socionext,uniphier-system-cache";
  60                 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
  61                 interrupts = <0 174 4>, <0 175 4>;
  62                 cache-unified;
  63                 cache-size = <(768 * 1024)>;
  64                 cache-sets = <256>;
  65                 cache-line-size = <128>;
  66                 cache-level = <2>;
  67         };
  68
  69         port0x: gpio@55000008 {
  70                 compatible = "socionext,uniphier-gpio";
  71                 reg = <0x55000008 0x8>;
  72                 gpio-controller;
  73                 #gpio-cells = <2>;
  74         };
  75
  76         port1x: gpio@55000010 {
  77                 compatible = "socionext,uniphier-gpio";
  78                 reg = <0x55000010 0x8>;
  79                 gpio-controller;
  80                 #gpio-cells = <2>;
  81         };
  82
  83         port2x: gpio@55000018 {
  84                 compatible = "socionext,uniphier-gpio";
  85                 reg = <0x55000018 0x8>;
  86                 gpio-controller;
  87                 #gpio-cells = <2>;
  88         };
  89
  90         port3x: gpio@55000020 {
  91                 compatible = "socionext,uniphier-gpio";
  92                 reg = <0x55000020 0x8>;
  93                 gpio-controller;
  94                 #gpio-cells = <2>;
  95         };
  96
  97         port4: gpio@55000028 {
  98                 compatible = "socionext,uniphier-gpio";
  99                 reg = <0x55000028 0x8>;
 100                 gpio-controller;
 101                 #gpio-cells = <2>;
 102         };
 103
 104         port5x: gpio@55000030 {
 105                 compatible = "socionext,uniphier-gpio";
 106                 reg = <0x55000030 0x8>;
 107                 gpio-controller;
 108                 #gpio-cells = <2>;
 109         };
 110
 111         port6x: gpio@55000038 {
 112                 compatible = "socionext,uniphier-gpio";
 113                 reg = <0x55000038 0x8>;
 114                 gpio-controller;
 115                 #gpio-cells = <2>;
 116         };
 117
 118         port7x: gpio@55000040 {
 119                 compatible = "socionext,uniphier-gpio";
 120                 reg = <0x55000040 0x8>;
 121                 gpio-controller;
 122                 #gpio-cells = <2>;
 123         };
 124
 125         port8x: gpio@55000048 {
 126                 compatible = "socionext,uniphier-gpio";
 127                 reg = <0x55000048 0x8>;
 128                 gpio-controller;
 129                 #gpio-cells = <2>;
 130         };
 131
 132         port9x: gpio@55000050 {
 133                 compatible = "socionext,uniphier-gpio";
 134                 reg = <0x55000050 0x8>;
 135                 gpio-controller;
 136                 #gpio-cells = <2>;
 137         };
 138
 139         port10x: gpio@55000058 {
 140                 compatible = "socionext,uniphier-gpio";
 141                 reg = <0x55000058 0x8>;
 142                 gpio-controller;
 143                 #gpio-cells = <2>;
 144         };
 145
 146         port11x: gpio@55000060 {
 147                 compatible = "socionext,uniphier-gpio";
 148                 reg = <0x55000060 0x8>;
 149                 gpio-controller;
 150                 #gpio-cells = <2>;
 151         };
 152
 153         port12x: gpio@55000068 {
 154                 compatible = "socionext,uniphier-gpio";
 155                 reg = <0x55000068 0x8>;
 156                 gpio-controller;
 157                 #gpio-cells = <2>;
 158         };
 159
 160         port13x: gpio@55000070 {
 161                 compatible = "socionext,uniphier-gpio";
 162                 reg = <0x55000070 0x8>;
 163                 gpio-controller;
 164                 #gpio-cells = <2>;
 165         };
 166
 167         port14x: gpio@55000078 {
 168                 compatible = "socionext,uniphier-gpio";
 169                 reg = <0x55000078 0x8>;
 170                 gpio-controller;
 171                 #gpio-cells = <2>;
 172         };
 173
 174         port17x: gpio@550000a0 {
 175                 compatible = "socionext,uniphier-gpio";
 176                 reg = <0x550000a0 0x8>;
 177                 gpio-controller;
 178                 #gpio-cells = <2>;
 179         };
 180
 181         port18x: gpio@550000a8 {
 182                 compatible = "socionext,uniphier-gpio";
 183                 reg = <0x550000a8 0x8>;
 184                 gpio-controller;
 185                 #gpio-cells = <2>;
 186         };
 187
 188         port19x: gpio@550000b0 {
 189                 compatible = "socionext,uniphier-gpio";
 190                 reg = <0x550000b0 0x8>;
 191                 gpio-controller;
 192                 #gpio-cells = <2>;
 193         };
 194
 195         port20x: gpio@550000b8 {
 196                 compatible = "socionext,uniphier-gpio";
 197                 reg = <0x550000b8 0x8>;
 198                 gpio-controller;
 199                 #gpio-cells = <2>;
 200         };
 201
 202         port21x: gpio@550000c0 {
 203                 compatible = "socionext,uniphier-gpio";
 204                 reg = <0x550000c0 0x8>;
 205                 gpio-controller;
 206                 #gpio-cells = <2>;
 207         };
 208
 209         port22x: gpio@550000c8 {
 210                 compatible = "socionext,uniphier-gpio";
 211                 reg = <0x550000c8 0x8>;
 212                 gpio-controller;
 213                 #gpio-cells = <2>;
 214         };
 215
 216         port23x: gpio@550000d0 {
 217                 compatible = "socionext,uniphier-gpio";
 218                 reg = <0x550000d0 0x8>;
 219                 gpio-controller;
 220                 #gpio-cells = <2>;
 221         };
 222
 223         port24x: gpio@550000d8 {
 224                 compatible = "socionext,uniphier-gpio";
 225                 reg = <0x550000d8 0x8>;
 226                 gpio-controller;
 227                 #gpio-cells = <2>;
 228         };
 229
 230         port25x: gpio@550000e0 {
 231                 compatible = "socionext,uniphier-gpio";
 232                 reg = <0x550000e0 0x8>;
 233                 gpio-controller;
 234                 #gpio-cells = <2>;
 235         };
 236
 237         port26x: gpio@550000e8 {
 238                 compatible = "socionext,uniphier-gpio";
 239                 reg = <0x550000e8 0x8>;
 240                 gpio-controller;
 241                 #gpio-cells = <2>;
 242         };
 243
 244         port27x: gpio@550000f0 {
 245                 compatible = "socionext,uniphier-gpio";
 246                 reg = <0x550000f0 0x8>;
 247                 gpio-controller;
 248                 #gpio-cells = <2>;
 249         };
 250
 251         port28x: gpio@550000f8 {
 252                 compatible = "socionext,uniphier-gpio";
 253                 reg = <0x550000f8 0x8>;
 254                 gpio-controller;
 255                 #gpio-cells = <2>;
 256         };
 257
 258         port29x: gpio@55000100 {
 259                 compatible = "socionext,uniphier-gpio";
 260                 reg = <0x55000100 0x8>;
 261                 gpio-controller;
 262                 #gpio-cells = <2>;
 263         };
 264
 265         port30x: gpio@55000108 {
 266                 compatible = "socionext,uniphier-gpio";
 267                 reg = <0x55000108 0x8>;
 268                 gpio-controller;
 269                 #gpio-cells = <2>;
 270         };
 271
 272         i2c0: i2c@58780000 {
 273                 compatible = "socionext,uniphier-fi2c";
 274                 status = "disabled";
 275                 reg = <0x58780000 0x80>;
 276                 #address-cells = <1>;
 277                 #size-cells = <0>;
 278                 interrupts = <0 41 4>;
 279                 pinctrl-names = "default";
 280                 pinctrl-0 = <&pinctrl_i2c0>;
 281                 clocks = <&i2c_clk>;
 282                 clock-frequency = <100000>;
 283         };
 284
 285         i2c1: i2c@58781000 {
 286                 compatible = "socionext,uniphier-fi2c";
 287                 status = "disabled";
 288                 reg = <0x58781000 0x80>;
 289                 #address-cells = <1>;
 290                 #size-cells = <0>;
 291                 interrupts = <0 42 4>;
 292                 pinctrl-names = "default";
 293                 pinctrl-0 = <&pinctrl_i2c1>;
 294                 clocks = <&i2c_clk>;
 295                 clock-frequency = <100000>;
 296         };
 297
 298         i2c2: i2c@58782000 {
 299                 compatible = "socionext,uniphier-fi2c";
 300                 status = "disabled";
 301                 reg = <0x58782000 0x80>;
 302                 #address-cells = <1>;
 303                 #size-cells = <0>;
 304                 interrupts = <0 43 4>;
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&pinctrl_i2c2>;
 307                 clocks = <&i2c_clk>;
 308                 clock-frequency = <100000>;
 309         };
 310
 311         i2c3: i2c@58783000 {
 312                 compatible = "socionext,uniphier-fi2c";
 313                 status = "disabled";
 314                 reg = <0x58783000 0x80>;
 315                 #address-cells = <1>;
 316                 #size-cells = <0>;
 317                 interrupts = <0 44 4>;
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&pinctrl_i2c3>;
 320                 clocks = <&i2c_clk>;
 321                 clock-frequency = <100000>;
 322         };
 323
 324         /* i2c4 does not exist */
 325
 326         /* chip-internal connection for DMD */
 327         i2c5: i2c@58785000 {
 328                 compatible = "socionext,uniphier-fi2c";
 329                 reg = <0x58785000 0x80>;
 330                 #address-cells = <1>;
 331                 #size-cells = <0>;
 332                 interrupts = <0 25 4>;
 333                 clocks = <&i2c_clk>;
 334                 clock-frequency = <400000>;
 335         };
 336
 337         /* chip-internal connection for HDMI */
 338         i2c6: i2c@58786000 {
 339                 compatible = "socionext,uniphier-fi2c";
 340                 reg = <0x58786000 0x80>;
 341                 #address-cells = <1>;
 342                 #size-cells = <0>;
 343                 interrupts = <0 26 4>;
 344                 clocks = <&i2c_clk>;
 345                 clock-frequency = <400000>;
 346         };
 347
 348         sd: sdhc@5a400000 {
 349                 compatible = "socionext,uniphier-sdhc";
 350                 status = "disabled";
 351                 reg = <0x5a400000 0x200>;
 352                 interrupts = <0 76 4>;
 353                 pinctrl-names = "default", "1.8v";
 354                 pinctrl-0 = <&pinctrl_sd>;
 355                 pinctrl-1 = <&pinctrl_sd_1v8>;
 356                 clocks = <&mio_clk 0>;
 357                 reset-names = "host", "bridge";
 358                 resets = <&mio_rst 0>, <&mio_rst 3>;
 359                 bus-width = <4>;
 360         };
 361
 362         emmc: sdhc@5a500000 {
 363                 compatible = "socionext,uniphier-sdhc";
 364                 status = "disabled";
 365                 reg = <0x5a500000 0x200>;
 366                 interrupts = <0 78 4>;
 367                 pinctrl-names = "default", "1.8v";
 368                 pinctrl-0 = <&pinctrl_emmc>;
 369                 pinctrl-1 = <&pinctrl_emmc_1v8>;
 370                 clocks = <&mio_clk 1>;
 371                 reset-names = "host", "bridge", "hw-reset";
 372                 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
 373                 bus-width = <8>;
 374                 non-removable;
 375         };
 376
 377         sd1: sdhc@5a600000 {
 378                 compatible = "socionext,uniphier-sdhc";
 379                 status = "disabled";
 380                 reg = <0x5a600000 0x200>;
 381                 interrupts = <0 85 4>;
 382                 pinctrl-names = "default", "1.8v";
 383                 pinctrl-0 = <&pinctrl_sd1>;
 384                 pinctrl-1 = <&pinctrl_sd1_1v8>;
 385                 clocks = <&mio_clk 2>;
 386                 resets = <&mio_rst 2>, <&mio_rst 5>;
 387                 bus-width = <4>;
 388         };
 389
 390         usb2: usb@5a800100 {
 391                 compatible = "socionext,uniphier-ehci", "generic-ehci";
 392                 status = "disabled";
 393                 reg = <0x5a800100 0x100>;
 394                 interrupts = <0 80 4>;
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&pinctrl_usb2>;
 397                 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
 398                 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 399                          <&mio_rst 12>;
 400         };
 401
 402         usb3: usb@5a810100 {
 403                 compatible = "socionext,uniphier-ehci", "generic-ehci";
 404                 status = "disabled";
 405                 reg = <0x5a810100 0x100>;
 406                 interrupts = <0 81 4>;
 407                 pinctrl-names = "default";
 408                 pinctrl-0 = <&pinctrl_usb3>;
 409                 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
 410                 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 411                          <&mio_rst 13>;
 412         };
 413
 414         aidet@5fc20000 {
 415                 compatible = "simple-mfd", "syscon";
 416                 reg = <0x5fc20000 0x200>;
 417         };
 418
 419         usb0: usb@65a00000 {
 420                 compatible = "socionext,uniphier-xhci", "generic-xhci";
 421                 status = "disabled";
 422                 reg = <0x65a00000 0x100>;
 423                 interrupts = <0 134 4>;
 424                 pinctrl-names = "default";
 425                 pinctrl-0 = <&pinctrl_usb0>;
 426         };
 427
 428         usb1: usb@65c00000 {
 429                 compatible = "socionext,uniphier-xhci", "generic-xhci";
 430                 status = "disabled";
 431                 reg = <0x65c00000 0x100>;
 432                 interrupts = <0 137 4>;
 433                 pinctrl-names = "default";
 434                 pinctrl-0 = <&pinctrl_usb1>;
 435         };
 436 };
 437
 438 &refclk {
 439         clock-frequency = <25000000>;
 440 };
 441
 442 &serial0 {
 443         clock-frequency = <73728000>;
 444 };
 445
 446 &serial1 {
 447         clock-frequency = <73728000>;
 448 };
 449
 450 &serial2 {
 451         clock-frequency = <73728000>;
 452 };
 453
 454 &serial3 {
 455         clock-frequency = <73728000>;
 456 };
 457
 458 &mio_clk {
 459         compatible = "socionext,uniphier-pro4-mio-clock";
 460 };
 461
 462 &mio_rst {
 463         compatible = "socionext,uniphier-pro4-mio-reset";
 464 };
 465
 466 &peri_clk {
 467         compatible = "socionext,uniphier-pro4-peri-clock";
 468 };
 469
 470 &peri_rst {
 471         compatible = "socionext,uniphier-pro4-peri-reset";
 472 };
 473
 474 &pinctrl {
 475         compatible = "socionext,uniphier-pro4-pinctrl";
 476 };
 477
 478 &sys_clk {
 479         compatible = "socionext,uniphier-pro4-clock";
 480 };
 481
 482 &sys_rst {
 483         compatible = "socionext,uniphier-pro4-reset";
 484 };