git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-pro4.dtsi

   1 /*
   2  * Device Tree Source for UniPhier Pro4 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 / {
  47         compatible = "socionext,uniphier-pro4";
  48         #address-cells = <1>;
  49         #size-cells = <1>;
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu@0 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a9";
  58                         reg = <0>;
  59                         enable-method = "psci";
  60                         next-level-cache = <&l2>;
  61                 };
  62
  63                 cpu@1 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a9";
  66                         reg = <1>;
  67                         enable-method = "psci";
  68                         next-level-cache = <&l2>;
  69                 };
  70         };
  71
  72         psci {
  73                 compatible = "arm,psci-0.2";
  74                 method = "smc";
  75         };
  76
  77         clocks {
  78                 refclk: ref {
  79                         compatible = "fixed-clock";
  80                         #clock-cells = <0>;
  81                         clock-frequency = <25000000>;
  82                 };
  83
  84                 arm_timer_clk: arm_timer_clk {
  85                         #clock-cells = <0>;
  86                         compatible = "fixed-clock";
  87                         clock-frequency = <50000000>;
  88                 };
  89         };
  90
  91         soc {
  92                 compatible = "simple-bus";
  93                 #address-cells = <1>;
  94                 #size-cells = <1>;
  95                 ranges;
  96                 interrupt-parent = <&intc>;
  97                 u-boot,dm-pre-reloc;
  98
  99                 l2: l2-cache@500c0000 {
 100                         compatible = "socionext,uniphier-system-cache";
 101                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
 102                               <0x506c0000 0x400>;
 103                         interrupts = <0 174 4>, <0 175 4>;
 104                         cache-unified;
 105                         cache-size = <(768 * 1024)>;
 106                         cache-sets = <256>;
 107                         cache-line-size = <128>;
 108                         cache-level = <2>;
 109                 };
 110
 111                 serial0: serial@54006800 {
 112                         compatible = "socionext,uniphier-uart";
 113                         status = "disabled";
 114                         reg = <0x54006800 0x40>;
 115                         interrupts = <0 33 4>;
 116                         pinctrl-names = "default";
 117                         pinctrl-0 = <&pinctrl_uart0>;
 118                         clocks = <&peri_clk 0>;
 119                         clock-frequency = <73728000>;
 120                 };
 121
 122                 serial1: serial@54006900 {
 123                         compatible = "socionext,uniphier-uart";
 124                         status = "disabled";
 125                         reg = <0x54006900 0x40>;
 126                         interrupts = <0 35 4>;
 127                         pinctrl-names = "default";
 128                         pinctrl-0 = <&pinctrl_uart1>;
 129                         clocks = <&peri_clk 1>;
 130                         clock-frequency = <73728000>;
 131                 };
 132
 133                 serial2: serial@54006a00 {
 134                         compatible = "socionext,uniphier-uart";
 135                         status = "disabled";
 136                         reg = <0x54006a00 0x40>;
 137                         interrupts = <0 37 4>;
 138                         pinctrl-names = "default";
 139                         pinctrl-0 = <&pinctrl_uart2>;
 140                         clocks = <&peri_clk 2>;
 141                         clock-frequency = <73728000>;
 142                 };
 143
 144                 serial3: serial@54006b00 {
 145                         compatible = "socionext,uniphier-uart";
 146                         status = "disabled";
 147                         reg = <0x54006b00 0x40>;
 148                         interrupts = <0 177 4>;
 149                         pinctrl-names = "default";
 150                         pinctrl-0 = <&pinctrl_uart3>;
 151                         clocks = <&peri_clk 3>;
 152                         clock-frequency = <73728000>;
 153                 };
 154
 155                 port0x: gpio@55000008 {
 156                         compatible = "socionext,uniphier-gpio";
 157                         reg = <0x55000008 0x8>;
 158                         gpio-controller;
 159                         #gpio-cells = <2>;
 160                 };
 161
 162                 port1x: gpio@55000010 {
 163                         compatible = "socionext,uniphier-gpio";
 164                         reg = <0x55000010 0x8>;
 165                         gpio-controller;
 166                         #gpio-cells = <2>;
 167                 };
 168
 169                 port2x: gpio@55000018 {
 170                         compatible = "socionext,uniphier-gpio";
 171                         reg = <0x55000018 0x8>;
 172                         gpio-controller;
 173                         #gpio-cells = <2>;
 174                 };
 175
 176                 port3x: gpio@55000020 {
 177                         compatible = "socionext,uniphier-gpio";
 178                         reg = <0x55000020 0x8>;
 179                         gpio-controller;
 180                         #gpio-cells = <2>;
 181                 };
 182
 183                 port4: gpio@55000028 {
 184                         compatible = "socionext,uniphier-gpio";
 185                         reg = <0x55000028 0x8>;
 186                         gpio-controller;
 187                         #gpio-cells = <2>;
 188                 };
 189
 190                 port5x: gpio@55000030 {
 191                         compatible = "socionext,uniphier-gpio";
 192                         reg = <0x55000030 0x8>;
 193                         gpio-controller;
 194                         #gpio-cells = <2>;
 195                 };
 196
 197                 port6x: gpio@55000038 {
 198                         compatible = "socionext,uniphier-gpio";
 199                         reg = <0x55000038 0x8>;
 200                         gpio-controller;
 201                         #gpio-cells = <2>;
 202                 };
 203
 204                 port7x: gpio@55000040 {
 205                         compatible = "socionext,uniphier-gpio";
 206                         reg = <0x55000040 0x8>;
 207                         gpio-controller;
 208                         #gpio-cells = <2>;
 209                 };
 210
 211                 port8x: gpio@55000048 {
 212                         compatible = "socionext,uniphier-gpio";
 213                         reg = <0x55000048 0x8>;
 214                         gpio-controller;
 215                         #gpio-cells = <2>;
 216                 };
 217
 218                 port9x: gpio@55000050 {
 219                         compatible = "socionext,uniphier-gpio";
 220                         reg = <0x55000050 0x8>;
 221                         gpio-controller;
 222                         #gpio-cells = <2>;
 223                 };
 224
 225                 port10x: gpio@55000058 {
 226                         compatible = "socionext,uniphier-gpio";
 227                         reg = <0x55000058 0x8>;
 228                         gpio-controller;
 229                         #gpio-cells = <2>;
 230                 };
 231
 232                 port11x: gpio@55000060 {
 233                         compatible = "socionext,uniphier-gpio";
 234                         reg = <0x55000060 0x8>;
 235                         gpio-controller;
 236                         #gpio-cells = <2>;
 237                 };
 238
 239                 port12x: gpio@55000068 {
 240                         compatible = "socionext,uniphier-gpio";
 241                         reg = <0x55000068 0x8>;
 242                         gpio-controller;
 243                         #gpio-cells = <2>;
 244                 };
 245
 246                 port13x: gpio@55000070 {
 247                         compatible = "socionext,uniphier-gpio";
 248                         reg = <0x55000070 0x8>;
 249                         gpio-controller;
 250                         #gpio-cells = <2>;
 251                 };
 252
 253                 port14x: gpio@55000078 {
 254                         compatible = "socionext,uniphier-gpio";
 255                         reg = <0x55000078 0x8>;
 256                         gpio-controller;
 257                         #gpio-cells = <2>;
 258                 };
 259
 260                 port17x: gpio@550000a0 {
 261                         compatible = "socionext,uniphier-gpio";
 262                         reg = <0x550000a0 0x8>;
 263                         gpio-controller;
 264                         #gpio-cells = <2>;
 265                 };
 266
 267                 port18x: gpio@550000a8 {
 268                         compatible = "socionext,uniphier-gpio";
 269                         reg = <0x550000a8 0x8>;
 270                         gpio-controller;
 271                         #gpio-cells = <2>;
 272                 };
 273
 274                 port19x: gpio@550000b0 {
 275                         compatible = "socionext,uniphier-gpio";
 276                         reg = <0x550000b0 0x8>;
 277                         gpio-controller;
 278                         #gpio-cells = <2>;
 279                 };
 280
 281                 port20x: gpio@550000b8 {
 282                         compatible = "socionext,uniphier-gpio";
 283                         reg = <0x550000b8 0x8>;
 284                         gpio-controller;
 285                         #gpio-cells = <2>;
 286                 };
 287
 288                 port21x: gpio@550000c0 {
 289                         compatible = "socionext,uniphier-gpio";
 290                         reg = <0x550000c0 0x8>;
 291                         gpio-controller;
 292                         #gpio-cells = <2>;
 293                 };
 294
 295                 port22x: gpio@550000c8 {
 296                         compatible = "socionext,uniphier-gpio";
 297                         reg = <0x550000c8 0x8>;
 298                         gpio-controller;
 299                         #gpio-cells = <2>;
 300                 };
 301
 302                 port23x: gpio@550000d0 {
 303                         compatible = "socionext,uniphier-gpio";
 304                         reg = <0x550000d0 0x8>;
 305                         gpio-controller;
 306                         #gpio-cells = <2>;
 307                 };
 308
 309                 port24x: gpio@550000d8 {
 310                         compatible = "socionext,uniphier-gpio";
 311                         reg = <0x550000d8 0x8>;
 312                         gpio-controller;
 313                         #gpio-cells = <2>;
 314                 };
 315
 316                 port25x: gpio@550000e0 {
 317                         compatible = "socionext,uniphier-gpio";
 318                         reg = <0x550000e0 0x8>;
 319                         gpio-controller;
 320                         #gpio-cells = <2>;
 321                 };
 322
 323                 port26x: gpio@550000e8 {
 324                         compatible = "socionext,uniphier-gpio";
 325                         reg = <0x550000e8 0x8>;
 326                         gpio-controller;
 327                         #gpio-cells = <2>;
 328                 };
 329
 330                 port27x: gpio@550000f0 {
 331                         compatible = "socionext,uniphier-gpio";
 332                         reg = <0x550000f0 0x8>;
 333                         gpio-controller;
 334                         #gpio-cells = <2>;
 335                 };
 336
 337                 port28x: gpio@550000f8 {
 338                         compatible = "socionext,uniphier-gpio";
 339                         reg = <0x550000f8 0x8>;
 340                         gpio-controller;
 341                         #gpio-cells = <2>;
 342                 };
 343
 344                 port29x: gpio@55000100 {
 345                         compatible = "socionext,uniphier-gpio";
 346                         reg = <0x55000100 0x8>;
 347                         gpio-controller;
 348                         #gpio-cells = <2>;
 349                 };
 350
 351                 port30x: gpio@55000108 {
 352                         compatible = "socionext,uniphier-gpio";
 353                         reg = <0x55000108 0x8>;
 354                         gpio-controller;
 355                         #gpio-cells = <2>;
 356                 };
 357
 358                 i2c0: i2c@58780000 {
 359                         compatible = "socionext,uniphier-fi2c";
 360                         status = "disabled";
 361                         reg = <0x58780000 0x80>;
 362                         #address-cells = <1>;
 363                         #size-cells = <0>;
 364                         interrupts = <0 41 4>;
 365                         pinctrl-names = "default";
 366                         pinctrl-0 = <&pinctrl_i2c0>;
 367                         clocks = <&peri_clk 4>;
 368                         clock-frequency = <100000>;
 369                 };
 370
 371                 i2c1: i2c@58781000 {
 372                         compatible = "socionext,uniphier-fi2c";
 373                         status = "disabled";
 374                         reg = <0x58781000 0x80>;
 375                         #address-cells = <1>;
 376                         #size-cells = <0>;
 377                         interrupts = <0 42 4>;
 378                         pinctrl-names = "default";
 379                         pinctrl-0 = <&pinctrl_i2c1>;
 380                         clocks = <&peri_clk 5>;
 381                         clock-frequency = <100000>;
 382                 };
 383
 384                 i2c2: i2c@58782000 {
 385                         compatible = "socionext,uniphier-fi2c";
 386                         status = "disabled";
 387                         reg = <0x58782000 0x80>;
 388                         #address-cells = <1>;
 389                         #size-cells = <0>;
 390                         interrupts = <0 43 4>;
 391                         pinctrl-names = "default";
 392                         pinctrl-0 = <&pinctrl_i2c2>;
 393                         clocks = <&peri_clk 6>;
 394                         clock-frequency = <100000>;
 395                 };
 396
 397                 i2c3: i2c@58783000 {
 398                         compatible = "socionext,uniphier-fi2c";
 399                         status = "disabled";
 400                         reg = <0x58783000 0x80>;
 401                         #address-cells = <1>;
 402                         #size-cells = <0>;
 403                         interrupts = <0 44 4>;
 404                         pinctrl-names = "default";
 405                         pinctrl-0 = <&pinctrl_i2c3>;
 406                         clocks = <&peri_clk 7>;
 407                         clock-frequency = <100000>;
 408                 };
 409
 410                 /* i2c4 does not exist */
 411
 412                 /* chip-internal connection for DMD */
 413                 i2c5: i2c@58785000 {
 414                         compatible = "socionext,uniphier-fi2c";
 415                         reg = <0x58785000 0x80>;
 416                         #address-cells = <1>;
 417                         #size-cells = <0>;
 418                         interrupts = <0 25 4>;
 419                         clocks = <&peri_clk 9>;
 420                         clock-frequency = <400000>;
 421                 };
 422
 423                 /* chip-internal connection for HDMI */
 424                 i2c6: i2c@58786000 {
 425                         compatible = "socionext,uniphier-fi2c";
 426                         reg = <0x58786000 0x80>;
 427                         #address-cells = <1>;
 428                         #size-cells = <0>;
 429                         interrupts = <0 26 4>;
 430                         clocks = <&peri_clk 10>;
 431                         clock-frequency = <400000>;
 432                 };
 433
 434                 system_bus: system-bus@58c00000 {
 435                         compatible = "socionext,uniphier-system-bus";
 436                         status = "disabled";
 437                         reg = <0x58c00000 0x400>;
 438                         #address-cells = <2>;
 439                         #size-cells = <1>;
 440                         pinctrl-names = "default";
 441                         pinctrl-0 = <&pinctrl_system_bus>;
 442                 };
 443
 444                 smpctrl@59801000 {
 445                         compatible = "socionext,uniphier-smpctrl";
 446                         reg = <0x59801000 0x400>;
 447                 };
 448
 449                 mioctrl@59810000 {
 450                         compatible = "socionext,uniphier-pro4-mioctrl",
 451                                      "simple-mfd", "syscon";
 452                         reg = <0x59810000 0x800>;
 453                         u-boot,dm-pre-reloc;
 454
 455                         mio_clk: clock {
 456                                 compatible = "socionext,uniphier-pro4-mio-clock";
 457                                 #clock-cells = <1>;
 458                         };
 459
 460                         mio_rst: reset {
 461                                 compatible = "socionext,uniphier-pro4-mio-reset";
 462                                 #reset-cells = <1>;
 463                         };
 464                 };
 465
 466                 perictrl@59820000 {
 467                         compatible = "socionext,uniphier-pro4-perictrl",
 468                                      "simple-mfd", "syscon";
 469                         reg = <0x59820000 0x200>;
 470
 471                         peri_clk: clock {
 472                                 compatible = "socionext,uniphier-pro4-peri-clock";
 473                                 #clock-cells = <1>;
 474                         };
 475
 476                         peri_rst: reset {
 477                                 compatible = "socionext,uniphier-pro4-peri-reset";
 478                                 #reset-cells = <1>;
 479                         };
 480                 };
 481
 482                 sd: sdhc@5a400000 {
 483                         compatible = "socionext,uniphier-sdhc";
 484                         status = "disabled";
 485                         reg = <0x5a400000 0x200>;
 486                         interrupts = <0 76 4>;
 487                         pinctrl-names = "default", "1.8v";
 488                         pinctrl-0 = <&pinctrl_sd>;
 489                         pinctrl-1 = <&pinctrl_sd_1v8>;
 490                         clocks = <&mio_clk 0>;
 491                         reset-names = "host", "bridge";
 492                         resets = <&mio_rst 0>, <&mio_rst 3>;
 493                         bus-width = <4>;
 494                         cap-sd-highspeed;
 495                         sd-uhs-sdr12;
 496                         sd-uhs-sdr25;
 497                         sd-uhs-sdr50;
 498                 };
 499
 500                 emmc: sdhc@5a500000 {
 501                         compatible = "socionext,uniphier-sdhc";
 502                         status = "disabled";
 503                         reg = <0x5a500000 0x200>;
 504                         interrupts = <0 78 4>;
 505                         pinctrl-names = "default", "1.8v";
 506                         pinctrl-0 = <&pinctrl_emmc>;
 507                         pinctrl-1 = <&pinctrl_emmc_1v8>;
 508                         clocks = <&mio_clk 1>;
 509                         reset-names = "host", "bridge";
 510                         resets = <&mio_rst 1>, <&mio_rst 4>;
 511                         bus-width = <8>;
 512                         non-removable;
 513                         cap-mmc-highspeed;
 514                         cap-mmc-hw-reset;
 515                 };
 516
 517                 sd1: sdhc@5a600000 {
 518                         compatible = "socionext,uniphier-sdhc";
 519                         status = "disabled";
 520                         reg = <0x5a600000 0x200>;
 521                         interrupts = <0 85 4>;
 522                         pinctrl-names = "default", "1.8v";
 523                         pinctrl-0 = <&pinctrl_sd1>;
 524                         pinctrl-1 = <&pinctrl_sd1_1v8>;
 525                         clocks = <&mio_clk 2>;
 526                         resets = <&mio_rst 2>, <&mio_rst 5>;
 527                         bus-width = <4>;
 528                         cap-sd-highspeed;
 529                         sd-uhs-sdr12;
 530                         sd-uhs-sdr25;
 531                         sd-uhs-sdr50;
 532                 };
 533
 534                 usb2: usb@5a800100 {
 535                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 536                         status = "disabled";
 537                         reg = <0x5a800100 0x100>;
 538                         interrupts = <0 80 4>;
 539                         pinctrl-names = "default";
 540                         pinctrl-0 = <&pinctrl_usb2>;
 541                         clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
 542                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 543                                  <&mio_rst 12>;
 544                 };
 545
 546                 usb3: usb@5a810100 {
 547                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 548                         status = "disabled";
 549                         reg = <0x5a810100 0x100>;
 550                         interrupts = <0 81 4>;
 551                         pinctrl-names = "default";
 552                         pinctrl-0 = <&pinctrl_usb3>;
 553                         clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
 554                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 555                                  <&mio_rst 13>;
 556                 };
 557
 558                 soc-glue@5f800000 {
 559                         compatible = "socionext,uniphier-pro4-soc-glue",
 560                                      "simple-mfd", "syscon";
 561                         reg = <0x5f800000 0x2000>;
 562                         u-boot,dm-pre-reloc;
 563
 564                         pinctrl: pinctrl {
 565                                 compatible = "socionext,uniphier-pro4-pinctrl";
 566                                 u-boot,dm-pre-reloc;
 567                         };
 568                 };
 569
 570                 aidet@5fc20000 {
 571                         compatible = "simple-mfd", "syscon";
 572                         reg = <0x5fc20000 0x200>;
 573                 };
 574
 575                 timer@60000200 {
 576                         compatible = "arm,cortex-a9-global-timer";
 577                         reg = <0x60000200 0x20>;
 578                         interrupts = <1 11 0x304>;
 579                         clocks = <&arm_timer_clk>;
 580                 };
 581
 582                 timer@60000600 {
 583                         compatible = "arm,cortex-a9-twd-timer";
 584                         reg = <0x60000600 0x20>;
 585                         interrupts = <1 13 0x304>;
 586                         clocks = <&arm_timer_clk>;
 587                 };
 588
 589                 intc: interrupt-controller@60001000 {
 590                         compatible = "arm,cortex-a9-gic";
 591                         reg = <0x60001000 0x1000>,
 592                               <0x60000100 0x100>;
 593                         #interrupt-cells = <3>;
 594                         interrupt-controller;
 595                 };
 596
 597                 sysctrl@61840000 {
 598                         compatible = "socionext,uniphier-pro4-sysctrl",
 599                                      "simple-mfd", "syscon";
 600                         reg = <0x61840000 0x10000>;
 601
 602                         sys_clk: clock {
 603                                 compatible = "socionext,uniphier-pro4-clock";
 604                                 #clock-cells = <1>;
 605                         };
 606
 607                         sys_rst: reset {
 608                                 compatible = "socionext,uniphier-pro4-reset";
 609                                 #reset-cells = <1>;
 610                         };
 611                 };
 612
 613                 usb0: usb@65b00000 {
 614                         compatible = "socionext,uniphier-pro4-dwc3";
 615                         status = "disabled";
 616                         reg = <0x65b00000 0x1000>;
 617                         #address-cells = <1>;
 618                         #size-cells = <1>;
 619                         ranges;
 620                         pinctrl-names = "default";
 621                         pinctrl-0 = <&pinctrl_usb0>;
 622                         dwc3@65a00000 {
 623                                 compatible = "snps,dwc3";
 624                                 reg = <0x65a00000 0x10000>;
 625                                 interrupts = <0 134 4>;
 626                                 tx-fifo-resize;
 627                         };
 628                 };
 629
 630                 usb1: usb@65d00000 {
 631                         compatible = "socionext,uniphier-pro4-dwc3";
 632                         status = "disabled";
 633                         reg = <0x65d00000 0x1000>;
 634                         #address-cells = <1>;
 635                         #size-cells = <1>;
 636                         ranges;
 637                         pinctrl-names = "default";
 638                         pinctrl-0 = <&pinctrl_usb1>;
 639                         dwc3@65c00000 {
 640                                 compatible = "snps,dwc3";
 641                                 reg = <0x65c00000 0x10000>;
 642                                 interrupts = <0 137 4>;
 643                                 tx-fifo-resize;
 644                         };
 645                 };
 646
 647                 nand: nand@68000000 {
 648                         compatible = "socionext,uniphier-denali-nand-v5a";
 649                         status = "disabled";
 650                         reg-names = "nand_data", "denali_reg";
 651                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 652                         interrupts = <0 65 4>;
 653                         pinctrl-names = "default";
 654                         pinctrl-0 = <&pinctrl_nand>;
 655                         clocks = <&sys_clk 2>;
 656                         nand-ecc-strength = <8>;
 657                 };
 658         };
 659 };
 660
 661 /include/ "uniphier-pinctrl.dtsi"