git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-pro5.dtsi

   1 /*
   2  * Device Tree Source for UniPhier Pro5 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 / {
  47         compatible = "socionext,uniphier-pro5";
  48         #address-cells = <1>;
  49         #size-cells = <1>;
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu@0 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a9";
  58                         reg = <0>;
  59                         clocks = <&sys_clk 32>;
  60                         enable-method = "psci";
  61                         next-level-cache = <&l2>;
  62                         operating-points-v2 = <&cpu_opp>;
  63                 };
  64
  65                 cpu@1 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a9";
  68                         reg = <1>;
  69                         clocks = <&sys_clk 32>;
  70                         enable-method = "psci";
  71                         next-level-cache = <&l2>;
  72                         operating-points-v2 = <&cpu_opp>;
  73                 };
  74         };
  75
  76         cpu_opp: opp_table {
  77                 compatible = "operating-points-v2";
  78                 opp-shared;
  79
  80                 opp-100000000 {
  81                         opp-hz = /bits/ 64 <100000000>;
  82                         clock-latency-ns = <300>;
  83                 };
  84                 opp-116667000 {
  85                         opp-hz = /bits/ 64 <116667000>;
  86                         clock-latency-ns = <300>;
  87                 };
  88                 opp-150000000 {
  89                         opp-hz = /bits/ 64 <150000000>;
  90                         clock-latency-ns = <300>;
  91                 };
  92                 opp-175000000 {
  93                         opp-hz = /bits/ 64 <175000000>;
  94                         clock-latency-ns = <300>;
  95                 };
  96                 opp-200000000 {
  97                         opp-hz = /bits/ 64 <200000000>;
  98                         clock-latency-ns = <300>;
  99                 };
 100                 opp-233334000 {
 101                         opp-hz = /bits/ 64 <233334000>;
 102                         clock-latency-ns = <300>;
 103                 };
 104                 opp-300000000 {
 105                         opp-hz = /bits/ 64 <300000000>;
 106                         clock-latency-ns = <300>;
 107                 };
 108                 opp-350000000 {
 109                         opp-hz = /bits/ 64 <350000000>;
 110                         clock-latency-ns = <300>;
 111                 };
 112                 opp-400000000 {
 113                         opp-hz = /bits/ 64 <400000000>;
 114                         clock-latency-ns = <300>;
 115                 };
 116                 opp-466667000 {
 117                         opp-hz = /bits/ 64 <466667000>;
 118                         clock-latency-ns = <300>;
 119                 };
 120                 opp-600000000 {
 121                         opp-hz = /bits/ 64 <600000000>;
 122                         clock-latency-ns = <300>;
 123                 };
 124                 opp-700000000 {
 125                         opp-hz = /bits/ 64 <700000000>;
 126                         clock-latency-ns = <300>;
 127                 };
 128                 opp-800000000 {
 129                         opp-hz = /bits/ 64 <800000000>;
 130                         clock-latency-ns = <300>;
 131                 };
 132                 opp-933334000 {
 133                         opp-hz = /bits/ 64 <933334000>;
 134                         clock-latency-ns = <300>;
 135                 };
 136                 opp-1200000000 {
 137                         opp-hz = /bits/ 64 <1200000000>;
 138                         clock-latency-ns = <300>;
 139                 };
 140                 opp-1400000000 {
 141                         opp-hz = /bits/ 64 <1400000000>;
 142                         clock-latency-ns = <300>;
 143                 };
 144         };
 145
 146         psci {
 147                 compatible = "arm,psci-0.2";
 148                 method = "smc";
 149         };
 150
 151         clocks {
 152                 refclk: ref {
 153                         compatible = "fixed-clock";
 154                         #clock-cells = <0>;
 155                         clock-frequency = <20000000>;
 156                 };
 157
 158                 arm_timer_clk: arm_timer_clk {
 159                         #clock-cells = <0>;
 160                         compatible = "fixed-clock";
 161                         clock-frequency = <50000000>;
 162                 };
 163         };
 164
 165         soc {
 166                 compatible = "simple-bus";
 167                 #address-cells = <1>;
 168                 #size-cells = <1>;
 169                 ranges;
 170                 interrupt-parent = <&intc>;
 171                 u-boot,dm-pre-reloc;
 172
 173                 l2: l2-cache@500c0000 {
 174                         compatible = "socionext,uniphier-system-cache";
 175                         reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
 176                               <0x506c0000 0x400>;
 177                         interrupts = <0 190 4>, <0 191 4>;
 178                         cache-unified;
 179                         cache-size = <(2 * 1024 * 1024)>;
 180                         cache-sets = <512>;
 181                         cache-line-size = <128>;
 182                         cache-level = <2>;
 183                         next-level-cache = <&l3>;
 184                 };
 185
 186                 l3: l3-cache@500c8000 {
 187                         compatible = "socionext,uniphier-system-cache";
 188                         reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
 189                               <0x506c8000 0x400>;
 190                         interrupts = <0 174 4>, <0 175 4>;
 191                         cache-unified;
 192                         cache-size = <(2 * 1024 * 1024)>;
 193                         cache-sets = <512>;
 194                         cache-line-size = <256>;
 195                         cache-level = <3>;
 196                 };
 197
 198                 serial0: serial@54006800 {
 199                         compatible = "socionext,uniphier-uart";
 200                         status = "disabled";
 201                         reg = <0x54006800 0x40>;
 202                         interrupts = <0 33 4>;
 203                         pinctrl-names = "default";
 204                         pinctrl-0 = <&pinctrl_uart0>;
 205                         clocks = <&peri_clk 0>;
 206                         clock-frequency = <73728000>;
 207                 };
 208
 209                 serial1: serial@54006900 {
 210                         compatible = "socionext,uniphier-uart";
 211                         status = "disabled";
 212                         reg = <0x54006900 0x40>;
 213                         interrupts = <0 35 4>;
 214                         pinctrl-names = "default";
 215                         pinctrl-0 = <&pinctrl_uart1>;
 216                         clocks = <&peri_clk 1>;
 217                         clock-frequency = <73728000>;
 218                 };
 219
 220                 serial2: serial@54006a00 {
 221                         compatible = "socionext,uniphier-uart";
 222                         status = "disabled";
 223                         reg = <0x54006a00 0x40>;
 224                         interrupts = <0 37 4>;
 225                         pinctrl-names = "default";
 226                         pinctrl-0 = <&pinctrl_uart2>;
 227                         clocks = <&peri_clk 2>;
 228                         clock-frequency = <73728000>;
 229                 };
 230
 231                 serial3: serial@54006b00 {
 232                         compatible = "socionext,uniphier-uart";
 233                         status = "disabled";
 234                         reg = <0x54006b00 0x40>;
 235                         interrupts = <0 177 4>;
 236                         pinctrl-names = "default";
 237                         pinctrl-0 = <&pinctrl_uart3>;
 238                         clocks = <&peri_clk 3>;
 239                         clock-frequency = <73728000>;
 240                 };
 241
 242                 port0x: gpio@55000008 {
 243                         compatible = "socionext,uniphier-gpio";
 244                         reg = <0x55000008 0x8>;
 245                         gpio-controller;
 246                         #gpio-cells = <2>;
 247                 };
 248
 249                 port1x: gpio@55000010 {
 250                         compatible = "socionext,uniphier-gpio";
 251                         reg = <0x55000010 0x8>;
 252                         gpio-controller;
 253                         #gpio-cells = <2>;
 254                 };
 255
 256                 port2x: gpio@55000018 {
 257                         compatible = "socionext,uniphier-gpio";
 258                         reg = <0x55000018 0x8>;
 259                         gpio-controller;
 260                         #gpio-cells = <2>;
 261                 };
 262
 263                 port3x: gpio@55000020 {
 264                         compatible = "socionext,uniphier-gpio";
 265                         reg = <0x55000020 0x8>;
 266                         gpio-controller;
 267                         #gpio-cells = <2>;
 268                 };
 269
 270                 port4: gpio@55000028 {
 271                         compatible = "socionext,uniphier-gpio";
 272                         reg = <0x55000028 0x8>;
 273                         gpio-controller;
 274                         #gpio-cells = <2>;
 275                 };
 276
 277                 port5x: gpio@55000030 {
 278                         compatible = "socionext,uniphier-gpio";
 279                         reg = <0x55000030 0x8>;
 280                         gpio-controller;
 281                         #gpio-cells = <2>;
 282                 };
 283
 284                 port6x: gpio@55000038 {
 285                         compatible = "socionext,uniphier-gpio";
 286                         reg = <0x55000038 0x8>;
 287                         gpio-controller;
 288                         #gpio-cells = <2>;
 289                 };
 290
 291                 port7x: gpio@55000040 {
 292                         compatible = "socionext,uniphier-gpio";
 293                         reg = <0x55000040 0x8>;
 294                         gpio-controller;
 295                         #gpio-cells = <2>;
 296                 };
 297
 298                 port8x: gpio@55000048 {
 299                         compatible = "socionext,uniphier-gpio";
 300                         reg = <0x55000048 0x8>;
 301                         gpio-controller;
 302                         #gpio-cells = <2>;
 303                 };
 304
 305                 port9x: gpio@55000050 {
 306                         compatible = "socionext,uniphier-gpio";
 307                         reg = <0x55000050 0x8>;
 308                         gpio-controller;
 309                         #gpio-cells = <2>;
 310                 };
 311
 312                 port10x: gpio@55000058 {
 313                         compatible = "socionext,uniphier-gpio";
 314                         reg = <0x55000058 0x8>;
 315                         gpio-controller;
 316                         #gpio-cells = <2>;
 317                 };
 318
 319                 port11x: gpio@55000060 {
 320                         compatible = "socionext,uniphier-gpio";
 321                         reg = <0x55000060 0x8>;
 322                         gpio-controller;
 323                         #gpio-cells = <2>;
 324                 };
 325
 326                 port12x: gpio@55000068 {
 327                         compatible = "socionext,uniphier-gpio";
 328                         reg = <0x55000068 0x8>;
 329                         gpio-controller;
 330                         #gpio-cells = <2>;
 331                 };
 332
 333                 port13x: gpio@55000070 {
 334                         compatible = "socionext,uniphier-gpio";
 335                         reg = <0x55000070 0x8>;
 336                         gpio-controller;
 337                         #gpio-cells = <2>;
 338                 };
 339
 340                 port14x: gpio@55000078 {
 341                         compatible = "socionext,uniphier-gpio";
 342                         reg = <0x55000078 0x8>;
 343                         gpio-controller;
 344                         #gpio-cells = <2>;
 345                 };
 346
 347                 port17x: gpio@550000a0 {
 348                         compatible = "socionext,uniphier-gpio";
 349                         reg = <0x550000a0 0x8>;
 350                         gpio-controller;
 351                         #gpio-cells = <2>;
 352                 };
 353
 354                 port18x: gpio@550000a8 {
 355                         compatible = "socionext,uniphier-gpio";
 356                         reg = <0x550000a8 0x8>;
 357                         gpio-controller;
 358                         #gpio-cells = <2>;
 359                 };
 360
 361                 port19x: gpio@550000b0 {
 362                         compatible = "socionext,uniphier-gpio";
 363                         reg = <0x550000b0 0x8>;
 364                         gpio-controller;
 365                         #gpio-cells = <2>;
 366                 };
 367
 368                 port20x: gpio@550000b8 {
 369                         compatible = "socionext,uniphier-gpio";
 370                         reg = <0x550000b8 0x8>;
 371                         gpio-controller;
 372                         #gpio-cells = <2>;
 373                 };
 374
 375                 port21x: gpio@550000c0 {
 376                         compatible = "socionext,uniphier-gpio";
 377                         reg = <0x550000c0 0x8>;
 378                         gpio-controller;
 379                         #gpio-cells = <2>;
 380                 };
 381
 382                 port22x: gpio@550000c8 {
 383                         compatible = "socionext,uniphier-gpio";
 384                         reg = <0x550000c8 0x8>;
 385                         gpio-controller;
 386                         #gpio-cells = <2>;
 387                 };
 388
 389                 port23x: gpio@550000d0 {
 390                         compatible = "socionext,uniphier-gpio";
 391                         reg = <0x550000d0 0x8>;
 392                         gpio-controller;
 393                         #gpio-cells = <2>;
 394                 };
 395
 396                 port24x: gpio@550000d8 {
 397                         compatible = "socionext,uniphier-gpio";
 398                         reg = <0x550000d8 0x8>;
 399                         gpio-controller;
 400                         #gpio-cells = <2>;
 401                 };
 402
 403                 port25x: gpio@550000e0 {
 404                         compatible = "socionext,uniphier-gpio";
 405                         reg = <0x550000e0 0x8>;
 406                         gpio-controller;
 407                         #gpio-cells = <2>;
 408                 };
 409
 410                 port26x: gpio@550000e8 {
 411                         compatible = "socionext,uniphier-gpio";
 412                         reg = <0x550000e8 0x8>;
 413                         gpio-controller;
 414                         #gpio-cells = <2>;
 415                 };
 416
 417                 port27x: gpio@550000f0 {
 418                         compatible = "socionext,uniphier-gpio";
 419                         reg = <0x550000f0 0x8>;
 420                         gpio-controller;
 421                         #gpio-cells = <2>;
 422                 };
 423
 424                 port28x: gpio@550000f8 {
 425                         compatible = "socionext,uniphier-gpio";
 426                         reg = <0x550000f8 0x8>;
 427                         gpio-controller;
 428                         #gpio-cells = <2>;
 429                 };
 430
 431                 port29x: gpio@55000100 {
 432                         compatible = "socionext,uniphier-gpio";
 433                         reg = <0x55000100 0x8>;
 434                         gpio-controller;
 435                         #gpio-cells = <2>;
 436                 };
 437
 438                 port30x: gpio@55000108 {
 439                         compatible = "socionext,uniphier-gpio";
 440                         reg = <0x55000108 0x8>;
 441                         gpio-controller;
 442                         #gpio-cells = <2>;
 443                 };
 444
 445                 i2c0: i2c@58780000 {
 446                         compatible = "socionext,uniphier-fi2c";
 447                         status = "disabled";
 448                         reg = <0x58780000 0x80>;
 449                         #address-cells = <1>;
 450                         #size-cells = <0>;
 451                         interrupts = <0 41 4>;
 452                         pinctrl-names = "default";
 453                         pinctrl-0 = <&pinctrl_i2c0>;
 454                         clocks = <&peri_clk 4>;
 455                         clock-frequency = <100000>;
 456                 };
 457
 458                 i2c1: i2c@58781000 {
 459                         compatible = "socionext,uniphier-fi2c";
 460                         status = "disabled";
 461                         reg = <0x58781000 0x80>;
 462                         #address-cells = <1>;
 463                         #size-cells = <0>;
 464                         interrupts = <0 42 4>;
 465                         pinctrl-names = "default";
 466                         pinctrl-0 = <&pinctrl_i2c1>;
 467                         clocks = <&peri_clk 5>;
 468                         clock-frequency = <100000>;
 469                 };
 470
 471                 i2c2: i2c@58782000 {
 472                         compatible = "socionext,uniphier-fi2c";
 473                         status = "disabled";
 474                         reg = <0x58782000 0x80>;
 475                         #address-cells = <1>;
 476                         #size-cells = <0>;
 477                         interrupts = <0 43 4>;
 478                         pinctrl-names = "default";
 479                         pinctrl-0 = <&pinctrl_i2c2>;
 480                         clocks = <&peri_clk 6>;
 481                         clock-frequency = <100000>;
 482                 };
 483
 484                 i2c3: i2c@58783000 {
 485                         compatible = "socionext,uniphier-fi2c";
 486                         status = "disabled";
 487                         reg = <0x58783000 0x80>;
 488                         #address-cells = <1>;
 489                         #size-cells = <0>;
 490                         interrupts = <0 44 4>;
 491                         pinctrl-names = "default";
 492                         pinctrl-0 = <&pinctrl_i2c3>;
 493                         clocks = <&peri_clk 7>;
 494                         clock-frequency = <100000>;
 495                 };
 496
 497                 /* i2c4 does not exist */
 498
 499                 /* chip-internal connection for DMD */
 500                 i2c5: i2c@58785000 {
 501                         compatible = "socionext,uniphier-fi2c";
 502                         reg = <0x58785000 0x80>;
 503                         #address-cells = <1>;
 504                         #size-cells = <0>;
 505                         interrupts = <0 25 4>;
 506                         clocks = <&peri_clk 9>;
 507                         clock-frequency = <400000>;
 508                 };
 509
 510                 /* chip-internal connection for HDMI */
 511                 i2c6: i2c@58786000 {
 512                         compatible = "socionext,uniphier-fi2c";
 513                         reg = <0x58786000 0x80>;
 514                         #address-cells = <1>;
 515                         #size-cells = <0>;
 516                         interrupts = <0 26 4>;
 517                         clocks = <&peri_clk 10>;
 518                         clock-frequency = <400000>;
 519                 };
 520
 521                 system_bus: system-bus@58c00000 {
 522                         compatible = "socionext,uniphier-system-bus";
 523                         status = "disabled";
 524                         reg = <0x58c00000 0x400>;
 525                         #address-cells = <2>;
 526                         #size-cells = <1>;
 527                         pinctrl-names = "default";
 528                         pinctrl-0 = <&pinctrl_system_bus>;
 529                 };
 530
 531                 smpctrl@59800000 {
 532                         compatible = "socionext,uniphier-smpctrl";
 533                         reg = <0x59801000 0x400>;
 534                 };
 535
 536                 sdctrl@59810000 {
 537                         compatible = "socionext,uniphier-pro5-sdctrl",
 538                                      "simple-mfd", "syscon";
 539                         reg = <0x59810000 0x800>;
 540                         u-boot,dm-pre-reloc;
 541
 542                         sd_clk: clock {
 543                                 compatible = "socionext,uniphier-pro5-sd-clock";
 544                                 #clock-cells = <1>;
 545                         };
 546
 547                         sd_rst: reset {
 548                                 compatible = "socionext,uniphier-pro5-sd-reset";
 549                                 #reset-cells = <1>;
 550                         };
 551                 };
 552
 553                 perictrl@59820000 {
 554                         compatible = "socionext,uniphier-pro5-perictrl",
 555                                      "simple-mfd", "syscon";
 556                         reg = <0x59820000 0x200>;
 557
 558                         peri_clk: clock {
 559                                 compatible = "socionext,uniphier-pro5-peri-clock";
 560                                 #clock-cells = <1>;
 561                         };
 562
 563                         peri_rst: reset {
 564                                 compatible = "socionext,uniphier-pro5-peri-reset";
 565                                 #reset-cells = <1>;
 566                         };
 567                 };
 568
 569                 soc-glue@5f800000 {
 570                         compatible = "socionext,uniphier-pro5-soc-glue",
 571                                      "simple-mfd", "syscon";
 572                         reg = <0x5f800000 0x2000>;
 573                         u-boot,dm-pre-reloc;
 574
 575                         pinctrl: pinctrl {
 576                                 compatible = "socionext,uniphier-pro5-pinctrl";
 577                                 u-boot,dm-pre-reloc;
 578                         };
 579                 };
 580
 581                 aidet@5fc20000 {
 582                         compatible = "simple-mfd", "syscon";
 583                         reg = <0x5fc20000 0x200>;
 584                 };
 585
 586                 timer@60000200 {
 587                         compatible = "arm,cortex-a9-global-timer";
 588                         reg = <0x60000200 0x20>;
 589                         interrupts = <1 11 0x304>;
 590                         clocks = <&arm_timer_clk>;
 591                 };
 592
 593                 timer@60000600 {
 594                         compatible = "arm,cortex-a9-twd-timer";
 595                         reg = <0x60000600 0x20>;
 596                         interrupts = <1 13 0x304>;
 597                         clocks = <&arm_timer_clk>;
 598                 };
 599
 600                 intc: interrupt-controller@60001000 {
 601                         compatible = "arm,cortex-a9-gic";
 602                         reg = <0x60001000 0x1000>,
 603                               <0x60000100 0x100>;
 604                         #interrupt-cells = <3>;
 605                         interrupt-controller;
 606                 };
 607
 608                 sysctrl@61840000 {
 609                         compatible = "socionext,uniphier-pro5-sysctrl",
 610                                      "simple-mfd", "syscon";
 611                         reg = <0x61840000 0x10000>;
 612
 613                         sys_clk: clock {
 614                                 compatible = "socionext,uniphier-pro5-clock";
 615                                 #clock-cells = <1>;
 616                         };
 617
 618                         sys_rst: reset {
 619                                 compatible = "socionext,uniphier-pro5-reset";
 620                                 #reset-cells = <1>;
 621                         };
 622                 };
 623
 624                 usb0: usb@65b00000 {
 625                         compatible = "socionext,uniphier-pro5-dwc3";
 626                         status = "disabled";
 627                         reg = <0x65b00000 0x1000>;
 628                         #address-cells = <1>;
 629                         #size-cells = <1>;
 630                         ranges;
 631                         pinctrl-names = "default";
 632                         pinctrl-0 = <&pinctrl_usb0>;
 633                         dwc3@65a00000 {
 634                                 compatible = "snps,dwc3";
 635                                 reg = <0x65a00000 0x10000>;
 636                                 interrupts = <0 134 4>;
 637                                 tx-fifo-resize;
 638                         };
 639                 };
 640
 641                 usb1: usb@65d00000 {
 642                         compatible = "socionext,uniphier-pro5-dwc3";
 643                         status = "disabled";
 644                         reg = <0x65d00000 0x1000>;
 645                         #address-cells = <1>;
 646                         #size-cells = <1>;
 647                         ranges;
 648                         pinctrl-names = "default";
 649                         pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
 650                         dwc3@65c00000 {
 651                                 compatible = "snps,dwc3";
 652                                 reg = <0x65c00000 0x10000>;
 653                                 interrupts = <0 137 4>;
 654                                 tx-fifo-resize;
 655                         };
 656                 };
 657
 658                 nand: nand@68000000 {
 659                         compatible = "socionext,uniphier-denali-nand-v5b";
 660                         status = "disabled";
 661                         reg-names = "nand_data", "denali_reg";
 662                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 663                         interrupts = <0 65 4>;
 664                         pinctrl-names = "default";
 665                         pinctrl-0 = <&pinctrl_nand>;
 666                         clocks = <&sys_clk 2>;
 667                         nand-ecc-strength = <8>;
 668                 };
 669
 670                 emmc: sdhc@68400000 {
 671                         compatible = "socionext,uniphier-sdhc";
 672                         status = "disabled";
 673                         reg = <0x68400000 0x800>;
 674                         interrupts = <0 78 4>;
 675                         pinctrl-names = "default";
 676                         pinctrl-0 = <&pinctrl_emmc>;
 677                         clocks = <&sd_clk 1>;
 678                         reset-names = "host";
 679                         resets = <&sd_rst 1>;
 680                         bus-width = <8>;
 681                         non-removable;
 682                         cap-mmc-highspeed;
 683                         cap-mmc-hw-reset;
 684                         no-3-3-v;
 685                 };
 686
 687                 sd: sdhc@68800000 {
 688                         compatible = "socionext,uniphier-sdhc";
 689                         status = "disabled";
 690                         reg = <0x68800000 0x800>;
 691                         interrupts = <0 76 4>;
 692                         pinctrl-names = "default", "1.8v";
 693                         pinctrl-0 = <&pinctrl_sd>;
 694                         pinctrl-1 = <&pinctrl_sd_1v8>;
 695                         clocks = <&sd_clk 0>;
 696                         reset-names = "host";
 697                         resets = <&sd_rst 0>;
 698                         bus-width = <4>;
 699                         cap-sd-highspeed;
 700                         sd-uhs-sdr12;
 701                         sd-uhs-sdr25;
 702                         sd-uhs-sdr50;
 703                 };
 704         };
 705 };
 706
 707 /include/ "uniphier-pinctrl.dtsi"