1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro5 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
9 compatible = "socionext,uniphier-pro5";
19 compatible = "arm,cortex-a9";
21 clocks = <&sys_clk 32>;
22 enable-method = "psci";
23 next-level-cache = <&l2>;
24 operating-points-v2 = <&cpu_opp>;
29 compatible = "arm,cortex-a9";
31 clocks = <&sys_clk 32>;
32 enable-method = "psci";
33 next-level-cache = <&l2>;
34 operating-points-v2 = <&cpu_opp>;
39 compatible = "operating-points-v2";
43 opp-hz = /bits/ 64 <100000000>;
44 clock-latency-ns = <300>;
47 opp-hz = /bits/ 64 <116667000>;
48 clock-latency-ns = <300>;
51 opp-hz = /bits/ 64 <150000000>;
52 clock-latency-ns = <300>;
55 opp-hz = /bits/ 64 <175000000>;
56 clock-latency-ns = <300>;
59 opp-hz = /bits/ 64 <200000000>;
60 clock-latency-ns = <300>;
63 opp-hz = /bits/ 64 <233334000>;
64 clock-latency-ns = <300>;
67 opp-hz = /bits/ 64 <300000000>;
68 clock-latency-ns = <300>;
71 opp-hz = /bits/ 64 <350000000>;
72 clock-latency-ns = <300>;
75 opp-hz = /bits/ 64 <400000000>;
76 clock-latency-ns = <300>;
79 opp-hz = /bits/ 64 <466667000>;
80 clock-latency-ns = <300>;
83 opp-hz = /bits/ 64 <600000000>;
84 clock-latency-ns = <300>;
87 opp-hz = /bits/ 64 <700000000>;
88 clock-latency-ns = <300>;
91 opp-hz = /bits/ 64 <800000000>;
92 clock-latency-ns = <300>;
95 opp-hz = /bits/ 64 <933334000>;
96 clock-latency-ns = <300>;
99 opp-hz = /bits/ 64 <1200000000>;
100 clock-latency-ns = <300>;
103 opp-hz = /bits/ 64 <1400000000>;
104 clock-latency-ns = <300>;
109 compatible = "arm,psci-0.2";
115 compatible = "fixed-clock";
117 clock-frequency = <20000000>;
120 arm_timer_clk: arm-timer {
122 compatible = "fixed-clock";
123 clock-frequency = <50000000>;
128 compatible = "simple-bus";
129 #address-cells = <1>;
132 interrupt-parent = <&intc>;
134 l2: l2-cache@500c0000 {
135 compatible = "socionext,uniphier-system-cache";
136 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
138 interrupts = <0 190 4>, <0 191 4>;
140 cache-size = <(2 * 1024 * 1024)>;
142 cache-line-size = <128>;
144 next-level-cache = <&l3>;
147 l3: l3-cache@500c8000 {
148 compatible = "socionext,uniphier-system-cache";
149 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
151 interrupts = <0 174 4>, <0 175 4>;
153 cache-size = <(2 * 1024 * 1024)>;
155 cache-line-size = <256>;
159 serial0: serial@54006800 {
160 compatible = "socionext,uniphier-uart";
162 reg = <0x54006800 0x40>;
163 interrupts = <0 33 4>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_uart0>;
166 clocks = <&peri_clk 0>;
167 clock-frequency = <73728000>;
168 resets = <&peri_rst 0>;
171 serial1: serial@54006900 {
172 compatible = "socionext,uniphier-uart";
174 reg = <0x54006900 0x40>;
175 interrupts = <0 35 4>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_uart1>;
178 clocks = <&peri_clk 1>;
179 clock-frequency = <73728000>;
180 resets = <&peri_rst 1>;
183 serial2: serial@54006a00 {
184 compatible = "socionext,uniphier-uart";
186 reg = <0x54006a00 0x40>;
187 interrupts = <0 37 4>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_uart2>;
190 clocks = <&peri_clk 2>;
191 clock-frequency = <73728000>;
192 resets = <&peri_rst 2>;
195 serial3: serial@54006b00 {
196 compatible = "socionext,uniphier-uart";
198 reg = <0x54006b00 0x40>;
199 interrupts = <0 177 4>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_uart3>;
202 clocks = <&peri_clk 3>;
203 clock-frequency = <73728000>;
204 resets = <&peri_rst 3>;
207 gpio: gpio@55000000 {
208 compatible = "socionext,uniphier-gpio";
209 reg = <0x55000000 0x200>;
210 interrupt-parent = <&aidet>;
211 interrupt-controller;
212 #interrupt-cells = <2>;
215 gpio-ranges = <&pinctrl 0 0 0>;
216 gpio-ranges-group-names = "gpio_range";
218 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
222 compatible = "socionext,uniphier-fi2c";
224 reg = <0x58780000 0x80>;
225 #address-cells = <1>;
227 interrupts = <0 41 4>;
228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_i2c0>;
230 clocks = <&peri_clk 4>;
231 resets = <&peri_rst 4>;
232 clock-frequency = <100000>;
236 compatible = "socionext,uniphier-fi2c";
238 reg = <0x58781000 0x80>;
239 #address-cells = <1>;
241 interrupts = <0 42 4>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_i2c1>;
244 clocks = <&peri_clk 5>;
245 resets = <&peri_rst 5>;
246 clock-frequency = <100000>;
250 compatible = "socionext,uniphier-fi2c";
252 reg = <0x58782000 0x80>;
253 #address-cells = <1>;
255 interrupts = <0 43 4>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_i2c2>;
258 clocks = <&peri_clk 6>;
259 resets = <&peri_rst 6>;
260 clock-frequency = <100000>;
264 compatible = "socionext,uniphier-fi2c";
266 reg = <0x58783000 0x80>;
267 #address-cells = <1>;
269 interrupts = <0 44 4>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_i2c3>;
272 clocks = <&peri_clk 7>;
273 resets = <&peri_rst 7>;
274 clock-frequency = <100000>;
277 /* i2c4 does not exist */
279 /* chip-internal connection for DMD */
281 compatible = "socionext,uniphier-fi2c";
282 reg = <0x58785000 0x80>;
283 #address-cells = <1>;
285 interrupts = <0 25 4>;
286 clocks = <&peri_clk 9>;
287 resets = <&peri_rst 9>;
288 clock-frequency = <400000>;
291 /* chip-internal connection for HDMI */
293 compatible = "socionext,uniphier-fi2c";
294 reg = <0x58786000 0x80>;
295 #address-cells = <1>;
297 interrupts = <0 26 4>;
298 clocks = <&peri_clk 10>;
299 resets = <&peri_rst 10>;
300 clock-frequency = <400000>;
303 system_bus: system-bus@58c00000 {
304 compatible = "socionext,uniphier-system-bus";
306 reg = <0x58c00000 0x400>;
307 #address-cells = <2>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_system_bus>;
314 compatible = "socionext,uniphier-smpctrl";
315 reg = <0x59801000 0x400>;
319 compatible = "socionext,uniphier-pro5-sdctrl",
320 "simple-mfd", "syscon";
321 reg = <0x59810000 0x400>;
324 compatible = "socionext,uniphier-pro5-sd-clock";
329 compatible = "socionext,uniphier-pro5-sd-reset";
335 compatible = "socionext,uniphier-pro5-perictrl",
336 "simple-mfd", "syscon";
337 reg = <0x59820000 0x200>;
340 compatible = "socionext,uniphier-pro5-peri-clock";
345 compatible = "socionext,uniphier-pro5-peri-reset";
351 compatible = "socionext,uniphier-pro5-soc-glue",
352 "simple-mfd", "syscon";
353 reg = <0x5f800000 0x2000>;
356 compatible = "socionext,uniphier-pro5-pinctrl";
361 compatible = "socionext,uniphier-pro5-soc-glue-debug",
363 #address-cells = <1>;
365 ranges = <0 0x5f900000 0x2000>;
368 compatible = "socionext,uniphier-efuse";
373 compatible = "socionext,uniphier-efuse";
378 compatible = "socionext,uniphier-efuse";
383 compatible = "socionext,uniphier-efuse";
388 compatible = "socionext,uniphier-efuse";
393 aidet: aidet@5fc20000 {
394 compatible = "socionext,uniphier-pro5-aidet";
395 reg = <0x5fc20000 0x200>;
396 interrupt-controller;
397 #interrupt-cells = <2>;
401 compatible = "arm,cortex-a9-global-timer";
402 reg = <0x60000200 0x20>;
403 interrupts = <1 11 0x304>;
404 clocks = <&arm_timer_clk>;
408 compatible = "arm,cortex-a9-twd-timer";
409 reg = <0x60000600 0x20>;
410 interrupts = <1 13 0x304>;
411 clocks = <&arm_timer_clk>;
414 intc: interrupt-controller@60001000 {
415 compatible = "arm,cortex-a9-gic";
416 reg = <0x60001000 0x1000>,
418 #interrupt-cells = <3>;
419 interrupt-controller;
423 compatible = "socionext,uniphier-pro5-sysctrl",
424 "simple-mfd", "syscon";
425 reg = <0x61840000 0x10000>;
428 compatible = "socionext,uniphier-pro5-clock";
433 compatible = "socionext,uniphier-pro5-reset";
439 compatible = "socionext,uniphier-pro5-dwc3";
441 reg = <0x65b00000 0x1000>;
442 #address-cells = <1>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&pinctrl_usb0>;
448 compatible = "snps,dwc3";
449 reg = <0x65a00000 0x10000>;
450 interrupts = <0 134 4>;
457 compatible = "socionext,uniphier-pro5-dwc3";
459 reg = <0x65d00000 0x1000>;
460 #address-cells = <1>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
466 compatible = "snps,dwc3";
467 reg = <0x65c00000 0x10000>;
468 interrupts = <0 137 4>;
474 nand: nand@68000000 {
475 compatible = "socionext,uniphier-denali-nand-v5b";
477 reg-names = "nand_data", "denali_reg";
478 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
479 interrupts = <0 65 4>;
480 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_nand2cs>;
482 clocks = <&sys_clk 2>;
483 resets = <&sys_rst 2>;
486 emmc: sdhc@68400000 {
487 compatible = "socionext,uniphier-sdhc";
489 reg = <0x68400000 0x800>;
490 interrupts = <0 78 4>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&pinctrl_emmc>;
493 clocks = <&sd_clk 1>;
494 reset-names = "host";
495 resets = <&sd_rst 1>;
504 compatible = "socionext,uniphier-sdhc";
506 reg = <0x68800000 0x800>;
507 interrupts = <0 76 4>;
508 pinctrl-names = "default", "1.8v";
509 pinctrl-0 = <&pinctrl_sd>;
510 pinctrl-1 = <&pinctrl_sd_1v8>;
511 clocks = <&sd_clk 0>;
512 reset-names = "host";
513 resets = <&sd_rst 0>;
523 #include "uniphier-pinctrl.dtsi"