2 * Device Tree Source for UniPhier Pro5 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-pro5";
21 compatible = "arm,cortex-a9";
23 clocks = <&sys_clk 32>;
24 enable-method = "psci";
25 next-level-cache = <&l2>;
26 operating-points-v2 = <&cpu_opp>;
31 compatible = "arm,cortex-a9";
33 clocks = <&sys_clk 32>;
34 enable-method = "psci";
35 next-level-cache = <&l2>;
36 operating-points-v2 = <&cpu_opp>;
41 compatible = "operating-points-v2";
45 opp-hz = /bits/ 64 <100000000>;
46 clock-latency-ns = <300>;
49 opp-hz = /bits/ 64 <116667000>;
50 clock-latency-ns = <300>;
53 opp-hz = /bits/ 64 <150000000>;
54 clock-latency-ns = <300>;
57 opp-hz = /bits/ 64 <175000000>;
58 clock-latency-ns = <300>;
61 opp-hz = /bits/ 64 <200000000>;
62 clock-latency-ns = <300>;
65 opp-hz = /bits/ 64 <233334000>;
66 clock-latency-ns = <300>;
69 opp-hz = /bits/ 64 <300000000>;
70 clock-latency-ns = <300>;
73 opp-hz = /bits/ 64 <350000000>;
74 clock-latency-ns = <300>;
77 opp-hz = /bits/ 64 <400000000>;
78 clock-latency-ns = <300>;
81 opp-hz = /bits/ 64 <466667000>;
82 clock-latency-ns = <300>;
85 opp-hz = /bits/ 64 <600000000>;
86 clock-latency-ns = <300>;
89 opp-hz = /bits/ 64 <700000000>;
90 clock-latency-ns = <300>;
93 opp-hz = /bits/ 64 <800000000>;
94 clock-latency-ns = <300>;
97 opp-hz = /bits/ 64 <933334000>;
98 clock-latency-ns = <300>;
101 opp-hz = /bits/ 64 <1200000000>;
102 clock-latency-ns = <300>;
105 opp-hz = /bits/ 64 <1400000000>;
106 clock-latency-ns = <300>;
111 compatible = "arm,psci-0.2";
117 compatible = "fixed-clock";
119 clock-frequency = <20000000>;
122 arm_timer_clk: arm-timer {
124 compatible = "fixed-clock";
125 clock-frequency = <50000000>;
130 compatible = "simple-bus";
131 #address-cells = <1>;
134 interrupt-parent = <&intc>;
136 l2: l2-cache@500c0000 {
137 compatible = "socionext,uniphier-system-cache";
138 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
140 interrupts = <0 190 4>, <0 191 4>;
142 cache-size = <(2 * 1024 * 1024)>;
144 cache-line-size = <128>;
146 next-level-cache = <&l3>;
149 l3: l3-cache@500c8000 {
150 compatible = "socionext,uniphier-system-cache";
151 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
153 interrupts = <0 174 4>, <0 175 4>;
155 cache-size = <(2 * 1024 * 1024)>;
157 cache-line-size = <256>;
161 serial0: serial@54006800 {
162 compatible = "socionext,uniphier-uart";
164 reg = <0x54006800 0x40>;
165 interrupts = <0 33 4>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_uart0>;
168 clocks = <&peri_clk 0>;
169 clock-frequency = <73728000>;
170 resets = <&peri_rst 0>;
173 serial1: serial@54006900 {
174 compatible = "socionext,uniphier-uart";
176 reg = <0x54006900 0x40>;
177 interrupts = <0 35 4>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_uart1>;
180 clocks = <&peri_clk 1>;
181 clock-frequency = <73728000>;
182 resets = <&peri_rst 1>;
185 serial2: serial@54006a00 {
186 compatible = "socionext,uniphier-uart";
188 reg = <0x54006a00 0x40>;
189 interrupts = <0 37 4>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_uart2>;
192 clocks = <&peri_clk 2>;
193 clock-frequency = <73728000>;
194 resets = <&peri_rst 2>;
197 serial3: serial@54006b00 {
198 compatible = "socionext,uniphier-uart";
200 reg = <0x54006b00 0x40>;
201 interrupts = <0 177 4>;
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_uart3>;
204 clocks = <&peri_clk 3>;
205 clock-frequency = <73728000>;
206 resets = <&peri_rst 3>;
209 gpio: gpio@55000000 {
210 compatible = "socionext,uniphier-gpio";
211 reg = <0x55000000 0x200>;
212 interrupt-parent = <&aidet>;
213 interrupt-controller;
214 #interrupt-cells = <2>;
217 gpio-ranges = <&pinctrl 0 0 0>;
218 gpio-ranges-group-names = "gpio_range";
220 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
224 compatible = "socionext,uniphier-fi2c";
226 reg = <0x58780000 0x80>;
227 #address-cells = <1>;
229 interrupts = <0 41 4>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_i2c0>;
232 clocks = <&peri_clk 4>;
233 resets = <&peri_rst 4>;
234 clock-frequency = <100000>;
238 compatible = "socionext,uniphier-fi2c";
240 reg = <0x58781000 0x80>;
241 #address-cells = <1>;
243 interrupts = <0 42 4>;
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_i2c1>;
246 clocks = <&peri_clk 5>;
247 resets = <&peri_rst 5>;
248 clock-frequency = <100000>;
252 compatible = "socionext,uniphier-fi2c";
254 reg = <0x58782000 0x80>;
255 #address-cells = <1>;
257 interrupts = <0 43 4>;
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_i2c2>;
260 clocks = <&peri_clk 6>;
261 resets = <&peri_rst 6>;
262 clock-frequency = <100000>;
266 compatible = "socionext,uniphier-fi2c";
268 reg = <0x58783000 0x80>;
269 #address-cells = <1>;
271 interrupts = <0 44 4>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_i2c3>;
274 clocks = <&peri_clk 7>;
275 resets = <&peri_rst 7>;
276 clock-frequency = <100000>;
279 /* i2c4 does not exist */
281 /* chip-internal connection for DMD */
283 compatible = "socionext,uniphier-fi2c";
284 reg = <0x58785000 0x80>;
285 #address-cells = <1>;
287 interrupts = <0 25 4>;
288 clocks = <&peri_clk 9>;
289 resets = <&peri_rst 9>;
290 clock-frequency = <400000>;
293 /* chip-internal connection for HDMI */
295 compatible = "socionext,uniphier-fi2c";
296 reg = <0x58786000 0x80>;
297 #address-cells = <1>;
299 interrupts = <0 26 4>;
300 clocks = <&peri_clk 10>;
301 resets = <&peri_rst 10>;
302 clock-frequency = <400000>;
305 system_bus: system-bus@58c00000 {
306 compatible = "socionext,uniphier-system-bus";
308 reg = <0x58c00000 0x400>;
309 #address-cells = <2>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_system_bus>;
316 compatible = "socionext,uniphier-smpctrl";
317 reg = <0x59801000 0x400>;
321 compatible = "socionext,uniphier-pro5-sdctrl",
322 "simple-mfd", "syscon";
323 reg = <0x59810000 0x400>;
326 compatible = "socionext,uniphier-pro5-sd-clock";
331 compatible = "socionext,uniphier-pro5-sd-reset";
337 compatible = "socionext,uniphier-pro5-perictrl",
338 "simple-mfd", "syscon";
339 reg = <0x59820000 0x200>;
342 compatible = "socionext,uniphier-pro5-peri-clock";
347 compatible = "socionext,uniphier-pro5-peri-reset";
353 compatible = "socionext,uniphier-pro5-soc-glue",
354 "simple-mfd", "syscon";
355 reg = <0x5f800000 0x2000>;
358 compatible = "socionext,uniphier-pro5-pinctrl";
362 aidet: aidet@5fc20000 {
363 compatible = "socionext,uniphier-pro5-aidet";
364 reg = <0x5fc20000 0x200>;
365 interrupt-controller;
366 #interrupt-cells = <2>;
370 compatible = "arm,cortex-a9-global-timer";
371 reg = <0x60000200 0x20>;
372 interrupts = <1 11 0x304>;
373 clocks = <&arm_timer_clk>;
377 compatible = "arm,cortex-a9-twd-timer";
378 reg = <0x60000600 0x20>;
379 interrupts = <1 13 0x304>;
380 clocks = <&arm_timer_clk>;
383 intc: interrupt-controller@60001000 {
384 compatible = "arm,cortex-a9-gic";
385 reg = <0x60001000 0x1000>,
387 #interrupt-cells = <3>;
388 interrupt-controller;
392 compatible = "socionext,uniphier-pro5-sysctrl",
393 "simple-mfd", "syscon";
394 reg = <0x61840000 0x10000>;
397 compatible = "socionext,uniphier-pro5-clock";
402 compatible = "socionext,uniphier-pro5-reset";
408 compatible = "socionext,uniphier-pro5-dwc3";
410 reg = <0x65b00000 0x1000>;
411 #address-cells = <1>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_usb0>;
417 compatible = "snps,dwc3";
418 reg = <0x65a00000 0x10000>;
419 interrupts = <0 134 4>;
426 compatible = "socionext,uniphier-pro5-dwc3";
428 reg = <0x65d00000 0x1000>;
429 #address-cells = <1>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
435 compatible = "snps,dwc3";
436 reg = <0x65c00000 0x10000>;
437 interrupts = <0 137 4>;
443 nand: nand@68000000 {
444 compatible = "socionext,uniphier-denali-nand-v5b";
446 reg-names = "nand_data", "denali_reg";
447 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
448 interrupts = <0 65 4>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_nand2cs>;
451 clocks = <&sys_clk 2>;
452 resets = <&sys_rst 2>;
455 emmc: sdhc@68400000 {
456 compatible = "socionext,uniphier-sdhc";
458 reg = <0x68400000 0x800>;
459 interrupts = <0 78 4>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&pinctrl_emmc>;
462 clocks = <&sd_clk 1>;
463 reset-names = "host";
464 resets = <&sd_rst 1>;
473 compatible = "socionext,uniphier-sdhc";
475 reg = <0x68800000 0x800>;
476 interrupts = <0 76 4>;
477 pinctrl-names = "default", "1.8v";
478 pinctrl-0 = <&pinctrl_sd>;
479 pinctrl-1 = <&pinctrl_sd_1v8>;
480 clocks = <&sd_clk 0>;
481 reset-names = "host";
482 resets = <&sd_rst 0>;
492 #include "uniphier-pinctrl.dtsi"