git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-pro5.dtsi

   1 /*
   2  * Device Tree Source for UniPhier Pro5 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 / {
  11         compatible = "socionext,uniphier-pro5";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         clocks = <&sys_clk 32>;
  24                         enable-method = "psci";
  25                         next-level-cache = <&l2>;
  26                         operating-points-v2 = <&cpu_opp>;
  27                 };
  28
  29                 cpu@1 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         reg = <1>;
  33                         clocks = <&sys_clk 32>;
  34                         enable-method = "psci";
  35                         next-level-cache = <&l2>;
  36                         operating-points-v2 = <&cpu_opp>;
  37                 };
  38         };
  39
  40         cpu_opp: opp_table {
  41                 compatible = "operating-points-v2";
  42                 opp-shared;
  43
  44                 opp-100000000 {
  45                         opp-hz = /bits/ 64 <100000000>;
  46                         clock-latency-ns = <300>;
  47                 };
  48                 opp-116667000 {
  49                         opp-hz = /bits/ 64 <116667000>;
  50                         clock-latency-ns = <300>;
  51                 };
  52                 opp-150000000 {
  53                         opp-hz = /bits/ 64 <150000000>;
  54                         clock-latency-ns = <300>;
  55                 };
  56                 opp-175000000 {
  57                         opp-hz = /bits/ 64 <175000000>;
  58                         clock-latency-ns = <300>;
  59                 };
  60                 opp-200000000 {
  61                         opp-hz = /bits/ 64 <200000000>;
  62                         clock-latency-ns = <300>;
  63                 };
  64                 opp-233334000 {
  65                         opp-hz = /bits/ 64 <233334000>;
  66                         clock-latency-ns = <300>;
  67                 };
  68                 opp-300000000 {
  69                         opp-hz = /bits/ 64 <300000000>;
  70                         clock-latency-ns = <300>;
  71                 };
  72                 opp-350000000 {
  73                         opp-hz = /bits/ 64 <350000000>;
  74                         clock-latency-ns = <300>;
  75                 };
  76                 opp-400000000 {
  77                         opp-hz = /bits/ 64 <400000000>;
  78                         clock-latency-ns = <300>;
  79                 };
  80                 opp-466667000 {
  81                         opp-hz = /bits/ 64 <466667000>;
  82                         clock-latency-ns = <300>;
  83                 };
  84                 opp-600000000 {
  85                         opp-hz = /bits/ 64 <600000000>;
  86                         clock-latency-ns = <300>;
  87                 };
  88                 opp-700000000 {
  89                         opp-hz = /bits/ 64 <700000000>;
  90                         clock-latency-ns = <300>;
  91                 };
  92                 opp-800000000 {
  93                         opp-hz = /bits/ 64 <800000000>;
  94                         clock-latency-ns = <300>;
  95                 };
  96                 opp-933334000 {
  97                         opp-hz = /bits/ 64 <933334000>;
  98                         clock-latency-ns = <300>;
  99                 };
 100                 opp-1200000000 {
 101                         opp-hz = /bits/ 64 <1200000000>;
 102                         clock-latency-ns = <300>;
 103                 };
 104                 opp-1400000000 {
 105                         opp-hz = /bits/ 64 <1400000000>;
 106                         clock-latency-ns = <300>;
 107                 };
 108         };
 109
 110         psci {
 111                 compatible = "arm,psci-0.2";
 112                 method = "smc";
 113         };
 114
 115         clocks {
 116                 refclk: ref {
 117                         compatible = "fixed-clock";
 118                         #clock-cells = <0>;
 119                         clock-frequency = <20000000>;
 120                 };
 121
 122                 arm_timer_clk: arm_timer_clk {
 123                         #clock-cells = <0>;
 124                         compatible = "fixed-clock";
 125                         clock-frequency = <50000000>;
 126                 };
 127         };
 128
 129         soc {
 130                 compatible = "simple-bus";
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133                 ranges;
 134                 interrupt-parent = <&intc>;
 135                 u-boot,dm-pre-reloc;
 136
 137                 l2: l2-cache@500c0000 {
 138                         compatible = "socionext,uniphier-system-cache";
 139                         reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
 140                               <0x506c0000 0x400>;
 141                         interrupts = <0 190 4>, <0 191 4>;
 142                         cache-unified;
 143                         cache-size = <(2 * 1024 * 1024)>;
 144                         cache-sets = <512>;
 145                         cache-line-size = <128>;
 146                         cache-level = <2>;
 147                         next-level-cache = <&l3>;
 148                 };
 149
 150                 l3: l3-cache@500c8000 {
 151                         compatible = "socionext,uniphier-system-cache";
 152                         reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
 153                               <0x506c8000 0x400>;
 154                         interrupts = <0 174 4>, <0 175 4>;
 155                         cache-unified;
 156                         cache-size = <(2 * 1024 * 1024)>;
 157                         cache-sets = <512>;
 158                         cache-line-size = <256>;
 159                         cache-level = <3>;
 160                 };
 161
 162                 serial0: serial@54006800 {
 163                         compatible = "socionext,uniphier-uart";
 164                         status = "disabled";
 165                         reg = <0x54006800 0x40>;
 166                         interrupts = <0 33 4>;
 167                         pinctrl-names = "default";
 168                         pinctrl-0 = <&pinctrl_uart0>;
 169                         clocks = <&peri_clk 0>;
 170                         clock-frequency = <73728000>;
 171                 };
 172
 173                 serial1: serial@54006900 {
 174                         compatible = "socionext,uniphier-uart";
 175                         status = "disabled";
 176                         reg = <0x54006900 0x40>;
 177                         interrupts = <0 35 4>;
 178                         pinctrl-names = "default";
 179                         pinctrl-0 = <&pinctrl_uart1>;
 180                         clocks = <&peri_clk 1>;
 181                         clock-frequency = <73728000>;
 182                 };
 183
 184                 serial2: serial@54006a00 {
 185                         compatible = "socionext,uniphier-uart";
 186                         status = "disabled";
 187                         reg = <0x54006a00 0x40>;
 188                         interrupts = <0 37 4>;
 189                         pinctrl-names = "default";
 190                         pinctrl-0 = <&pinctrl_uart2>;
 191                         clocks = <&peri_clk 2>;
 192                         clock-frequency = <73728000>;
 193                 };
 194
 195                 serial3: serial@54006b00 {
 196                         compatible = "socionext,uniphier-uart";
 197                         status = "disabled";
 198                         reg = <0x54006b00 0x40>;
 199                         interrupts = <0 177 4>;
 200                         pinctrl-names = "default";
 201                         pinctrl-0 = <&pinctrl_uart3>;
 202                         clocks = <&peri_clk 3>;
 203                         clock-frequency = <73728000>;
 204                 };
 205
 206                 gpio: gpio@55000000 {
 207                         compatible = "socionext,uniphier-gpio";
 208                         reg = <0x55000000 0x200>;
 209                         interrupt-parent = <&aidet>;
 210                         interrupt-controller;
 211                         #interrupt-cells = <2>;
 212                         gpio-controller;
 213                         #gpio-cells = <2>;
 214                         gpio-ranges = <&pinctrl 0 0 0>;
 215                         gpio-ranges-group-names = "gpio_range";
 216                         ngpios = <248>;
 217                 };
 218
 219                 i2c0: i2c@58780000 {
 220                         compatible = "socionext,uniphier-fi2c";
 221                         status = "disabled";
 222                         reg = <0x58780000 0x80>;
 223                         #address-cells = <1>;
 224                         #size-cells = <0>;
 225                         interrupts = <0 41 4>;
 226                         pinctrl-names = "default";
 227                         pinctrl-0 = <&pinctrl_i2c0>;
 228                         clocks = <&peri_clk 4>;
 229                         clock-frequency = <100000>;
 230                 };
 231
 232                 i2c1: i2c@58781000 {
 233                         compatible = "socionext,uniphier-fi2c";
 234                         status = "disabled";
 235                         reg = <0x58781000 0x80>;
 236                         #address-cells = <1>;
 237                         #size-cells = <0>;
 238                         interrupts = <0 42 4>;
 239                         pinctrl-names = "default";
 240                         pinctrl-0 = <&pinctrl_i2c1>;
 241                         clocks = <&peri_clk 5>;
 242                         clock-frequency = <100000>;
 243                 };
 244
 245                 i2c2: i2c@58782000 {
 246                         compatible = "socionext,uniphier-fi2c";
 247                         status = "disabled";
 248                         reg = <0x58782000 0x80>;
 249                         #address-cells = <1>;
 250                         #size-cells = <0>;
 251                         interrupts = <0 43 4>;
 252                         pinctrl-names = "default";
 253                         pinctrl-0 = <&pinctrl_i2c2>;
 254                         clocks = <&peri_clk 6>;
 255                         clock-frequency = <100000>;
 256                 };
 257
 258                 i2c3: i2c@58783000 {
 259                         compatible = "socionext,uniphier-fi2c";
 260                         status = "disabled";
 261                         reg = <0x58783000 0x80>;
 262                         #address-cells = <1>;
 263                         #size-cells = <0>;
 264                         interrupts = <0 44 4>;
 265                         pinctrl-names = "default";
 266                         pinctrl-0 = <&pinctrl_i2c3>;
 267                         clocks = <&peri_clk 7>;
 268                         clock-frequency = <100000>;
 269                 };
 270
 271                 /* i2c4 does not exist */
 272
 273                 /* chip-internal connection for DMD */
 274                 i2c5: i2c@58785000 {
 275                         compatible = "socionext,uniphier-fi2c";
 276                         reg = <0x58785000 0x80>;
 277                         #address-cells = <1>;
 278                         #size-cells = <0>;
 279                         interrupts = <0 25 4>;
 280                         clocks = <&peri_clk 9>;
 281                         clock-frequency = <400000>;
 282                 };
 283
 284                 /* chip-internal connection for HDMI */
 285                 i2c6: i2c@58786000 {
 286                         compatible = "socionext,uniphier-fi2c";
 287                         reg = <0x58786000 0x80>;
 288                         #address-cells = <1>;
 289                         #size-cells = <0>;
 290                         interrupts = <0 26 4>;
 291                         clocks = <&peri_clk 10>;
 292                         clock-frequency = <400000>;
 293                 };
 294
 295                 system_bus: system-bus@58c00000 {
 296                         compatible = "socionext,uniphier-system-bus";
 297                         status = "disabled";
 298                         reg = <0x58c00000 0x400>;
 299                         #address-cells = <2>;
 300                         #size-cells = <1>;
 301                         pinctrl-names = "default";
 302                         pinctrl-0 = <&pinctrl_system_bus>;
 303                 };
 304
 305                 smpctrl@59801000 {
 306                         compatible = "socionext,uniphier-smpctrl";
 307                         reg = <0x59801000 0x400>;
 308                 };
 309
 310                 sdctrl@59810000 {
 311                         compatible = "socionext,uniphier-pro5-sdctrl",
 312                                      "simple-mfd", "syscon";
 313                         reg = <0x59810000 0x400>;
 314                         u-boot,dm-pre-reloc;
 315
 316                         sd_clk: clock {
 317                                 compatible = "socionext,uniphier-pro5-sd-clock";
 318                                 #clock-cells = <1>;
 319                         };
 320
 321                         sd_rst: reset {
 322                                 compatible = "socionext,uniphier-pro5-sd-reset";
 323                                 #reset-cells = <1>;
 324                         };
 325                 };
 326
 327                 perictrl@59820000 {
 328                         compatible = "socionext,uniphier-pro5-perictrl",
 329                                      "simple-mfd", "syscon";
 330                         reg = <0x59820000 0x200>;
 331
 332                         peri_clk: clock {
 333                                 compatible = "socionext,uniphier-pro5-peri-clock";
 334                                 #clock-cells = <1>;
 335                         };
 336
 337                         peri_rst: reset {
 338                                 compatible = "socionext,uniphier-pro5-peri-reset";
 339                                 #reset-cells = <1>;
 340                         };
 341                 };
 342
 343                 soc-glue@5f800000 {
 344                         compatible = "socionext,uniphier-pro5-soc-glue",
 345                                      "simple-mfd", "syscon";
 346                         reg = <0x5f800000 0x2000>;
 347                         u-boot,dm-pre-reloc;
 348
 349                         pinctrl: pinctrl {
 350                                 compatible = "socionext,uniphier-pro5-pinctrl";
 351                                 u-boot,dm-pre-reloc;
 352                         };
 353                 };
 354
 355                 aidet: aidet@5fc20000 {
 356                         compatible = "socionext,uniphier-pro5-aidet";
 357                         reg = <0x5fc20000 0x200>;
 358                         interrupt-controller;
 359                         #interrupt-cells = <2>;
 360                 };
 361
 362                 timer@60000200 {
 363                         compatible = "arm,cortex-a9-global-timer";
 364                         reg = <0x60000200 0x20>;
 365                         interrupts = <1 11 0x304>;
 366                         clocks = <&arm_timer_clk>;
 367                 };
 368
 369                 timer@60000600 {
 370                         compatible = "arm,cortex-a9-twd-timer";
 371                         reg = <0x60000600 0x20>;
 372                         interrupts = <1 13 0x304>;
 373                         clocks = <&arm_timer_clk>;
 374                 };
 375
 376                 intc: interrupt-controller@60001000 {
 377                         compatible = "arm,cortex-a9-gic";
 378                         reg = <0x60001000 0x1000>,
 379                               <0x60000100 0x100>;
 380                         #interrupt-cells = <3>;
 381                         interrupt-controller;
 382                 };
 383
 384                 sysctrl@61840000 {
 385                         compatible = "socionext,uniphier-pro5-sysctrl",
 386                                      "simple-mfd", "syscon";
 387                         reg = <0x61840000 0x10000>;
 388
 389                         sys_clk: clock {
 390                                 compatible = "socionext,uniphier-pro5-clock";
 391                                 #clock-cells = <1>;
 392                         };
 393
 394                         sys_rst: reset {
 395                                 compatible = "socionext,uniphier-pro5-reset";
 396                                 #reset-cells = <1>;
 397                         };
 398                 };
 399
 400                 usb0: usb@65b00000 {
 401                         compatible = "socionext,uniphier-pro5-dwc3";
 402                         status = "disabled";
 403                         reg = <0x65b00000 0x1000>;
 404                         #address-cells = <1>;
 405                         #size-cells = <1>;
 406                         ranges;
 407                         pinctrl-names = "default";
 408                         pinctrl-0 = <&pinctrl_usb0>;
 409                         dwc3@65a00000 {
 410                                 compatible = "snps,dwc3";
 411                                 reg = <0x65a00000 0x10000>;
 412                                 interrupts = <0 134 4>;
 413                                 dr_mode = "host";
 414                                 tx-fifo-resize;
 415                         };
 416                 };
 417
 418                 usb1: usb@65d00000 {
 419                         compatible = "socionext,uniphier-pro5-dwc3";
 420                         status = "disabled";
 421                         reg = <0x65d00000 0x1000>;
 422                         #address-cells = <1>;
 423                         #size-cells = <1>;
 424                         ranges;
 425                         pinctrl-names = "default";
 426                         pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
 427                         dwc3@65c00000 {
 428                                 compatible = "snps,dwc3";
 429                                 reg = <0x65c00000 0x10000>;
 430                                 interrupts = <0 137 4>;
 431                                 dr_mode = "host";
 432                                 tx-fifo-resize;
 433                         };
 434                 };
 435
 436                 nand: nand@68000000 {
 437                         compatible = "socionext,uniphier-denali-nand-v5b";
 438                         status = "disabled";
 439                         reg-names = "nand_data", "denali_reg";
 440                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 441                         interrupts = <0 65 4>;
 442                         pinctrl-names = "default";
 443                         pinctrl-0 = <&pinctrl_nand2cs>;
 444                         clocks = <&sys_clk 2>;
 445                 };
 446
 447                 emmc: sdhc@68400000 {
 448                         compatible = "socionext,uniphier-sdhc";
 449                         status = "disabled";
 450                         reg = <0x68400000 0x800>;
 451                         interrupts = <0 78 4>;
 452                         pinctrl-names = "default";
 453                         pinctrl-0 = <&pinctrl_emmc>;
 454                         clocks = <&sd_clk 1>;
 455                         reset-names = "host";
 456                         resets = <&sd_rst 1>;
 457                         bus-width = <8>;
 458                         non-removable;
 459                         cap-mmc-highspeed;
 460                         cap-mmc-hw-reset;
 461                         no-3-3-v;
 462                 };
 463
 464                 sd: sdhc@68800000 {
 465                         compatible = "socionext,uniphier-sdhc";
 466                         status = "disabled";
 467                         reg = <0x68800000 0x800>;
 468                         interrupts = <0 76 4>;
 469                         pinctrl-names = "default", "1.8v";
 470                         pinctrl-0 = <&pinctrl_sd>;
 471                         pinctrl-1 = <&pinctrl_sd_1v8>;
 472                         clocks = <&sd_clk 0>;
 473                         reset-names = "host";
 474                         resets = <&sd_rst 0>;
 475                         bus-width = <4>;
 476                         cap-sd-highspeed;
 477                         sd-uhs-sdr12;
 478                         sd-uhs-sdr25;
 479                         sd-uhs-sdr50;
 480                 };
 481         };
 482 };
 483
 484 #include "uniphier-pinctrl.dtsi"